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Showing results 9 to 17 of 17

Fault Coverage and Resource Analysis for Diverse Structures of Clock TSV Fault-Tolerant Units in 3D ICs

Park, Heechun , Kim, Taewhan

Conference Paper Issue Date2013-11-17 View24
Hybrid asynchronous circuit generation amenable to conventional EDA flow File

Park , Heechun , Kim, Taewhan

Article Issue Date2019-01 View35
Minimum Implant Area-Aware Threshold Voltage Refinement in Pre-Placement

Jeong, Eunsol , Park, Heechun , Kim, Taewhan

Conference Paper Issue Date2021-08-09 View26
Size-dependent antibiotic effect of graphene oxide

Kim, Ungsoo , Park, Kwang Hyun , Lee, Junghyun , Kim, Taewhan , Kwon, Heeyun , Mitchell, Robert J. , Yang, Changduk , Park, Hyesung

Conference Paper Issue Date2017-04-06 View46
Speeding-up neuromorphic computation for neural networks: Structure optimization approach File

Park , Heechun , Kim, Taewhan

Article Issue Date2022-01 View40
Structure Optimizations of Neuromorphic Computing Architectures for Deep Neural Networks

Park, Heechun , Kim, Taewhan

Conference Paper Issue Date2018-03-19 View28
Synthesis of TSV Fault-Tolerant 3-D Clock Trees File

Park, Heechun , Kim, Taewhan

Article Issue Date2015-02 View44
Synthesizing Asynchronous Circuits Toward Practical Use File

Park, Heechun , Kim, Taewhan

Conference Paper Issue Date2016-07-11 View32
비동기식 회로 설계 구조에 대한 전력 및 면적 비교

Park, Heechun , Kim, Taewhan

Conference Paper Issue Date2015-11-27 View22
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