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Showing results 1 to 8 of 8

A Low-Jitter and Low-Fractional-Spur Ring-DCO-Based Fractional-N Digital PLL Using a DTC's Second-/Third-Order Nonlinearity Cancellation and a Probability-Density-Shaping Delta sigma M File

Hwang, Chanwoong , Park, Hangi , Lee, Yongsun , Seong, Taeho , Choi, Jaehyouk

Article Issue Date2022-09 View17
A Low-Jitter and Low-Reference-Spur Ring-VCO- Based Injection-Locked Clock Multiplier Using a Triple-Point Background Calibrator File

Yoo, Seyeon , Choi, Seojin , Lee, Yongsun , Seong, Taeho , Lim, Younghyun , Choi, Jaehyouk

Article Issue Date2021-01 View8
A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Switched-Loop Filter PLL Using a Fast Phase-Error Correction Technique File

Lee, Yongsun , Seong, Taeho , Yoo, Seyeon , Choi, Jaehyouk

Article Issue Date2018-04 View9
A Low-Jitter Injection-Locked Multi-Frequency Generator Using Digitally Controlled Oscillators and Time-Interleaved Calibration File

Yoon, Heein , Park, Suneui , Choi, Jaehyouk

Article Issue Date2019-06 View14
An Ultra-Low-Jitter, mmW-Band Frequency Synthesizer Based on Digital Subsampling PLL Using Optimally Spaced Voltage Comparators File

Kim, Juyeop , Lim, Younghyun , Yoon, Heein , Lee, Yongsun , Park, Hangi , Cho, Yoonseo , Seong, Taeho , Choi, Jaehyouk

Article Issue Date2019-12 View19
Improved Target Impedance Concept With Jitter Specification File

Sun, Yin , Kim, Jingook , Ouyang, Muqi , Hwang, Chulsoon

Article Issue Date2020-08 View11
Measurement and Analysis of System-Level ESD-Induced Jitter in a Delay-Locked Loop File

Jeong, Myeongjo , Shin, Minchul , Kim, Jinwoo , Seung, Manho , Lee, Seokkiu , Kim, Jingook

Article Issue Date2020-10 View15
On-chip linear voltage regulator module (VRM) effect on power distribution network (PDN) noise and jitter at high-speed output buffer File

Kim, Heegon , Kim, Sukjin , Kim, Joungho , Yoon, Changwook , Achkir, Brice , Fan, Jun

Article Issue Date2015-08 View9
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