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Kim, Youngmin
Nano-scale(system) Design & Automation Lab
Research Interests
  • Design & Technology Co-Optimization (DTCO)

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TSV Geometrical Variations and Optimization Metric with Repeaters for 3D IC

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Title
TSV Geometrical Variations and Optimization Metric with Repeaters for 3D IC
Author
Nguyen, Hung Viet Ryu, MyunghwanKim, Youngmin
Keywords
3d systems;  Coupling effect;  Delay;  Electrical models;  Geometrical factors;  Geometrical variations;  Interconnect;  Monte Carlo Simulation;  MOS-FET;  Optimal number;  Power;  Process Variation;  Ring oscillator;  Through-Silicon-Via
Issue Date
201212
Publisher
IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
Citation
IEICE TRANSACTIONS ON ELECTRONICS, v.E95C, no.12, pp.1864 - 1871
Abstract
This paper evaluates the impact of Through-Silicon Via (TSV) on the performance and power consumption of 3D circuitry. The physical and electrical model of TSV which considers the coupling effects with adjacent TSVs is exploited in our investigation. Simulation results show that the overall performance of 3D IC infused with TSV can be improved noticeably. The frequency of the ring oscillator in 4-tier stacking layout soars up to two times compared with one in 2D planar. Furthermore, TSV process variations are examined by Monte Carlo simulations to figure out the geometrical factor having more impact in manufacturing. An in-depth research on repeater associated with TSV offers a metric to compute the optimization of 3D systems integration in terms of performance and energy dissipation. By such optimization metric with 45 nm MOSFET used in our circuit layout, it is found that the optimal number of tiers in both performance and power consumption approaches 4 since the substantial TSV-TSV coupling effect in the worst case of interference is expected in 3D IC.
URI
http://scholarworks.unist.ac.kr/handle/201301/2534
DOI
http://dx.doi.org/10.1587/transele.E95.C.1864
ISSN
0916-8524
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ECE_Journal Papers
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