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Showing results 1 to 20 of 21

Issue DateTitleAuthor(s)TypeView
2013A high resolution and high linearity 45 nm CMOS fully digital voltage sensor for low power applicationsRyu, Myunghwan; Kim, YoungminARTICLE365
201202A novel methodology for speeding up IC performance in 32nm FinFETNguyen, Hung Viet; Ryu, Myunghwan; Kim, YoungminARTICLE288
201410A performance analysis for interconnections of 3D ICs with frequency-dependent TSV model in S-parameterHan, Ki Jin; Lim, Younghyun; Kim, YoungminARTICLE362
201509A Wide Range On-Chip Leakage Sensor Using a Current-Frequency Converting Technique in 65-nm Technology NodeChoi, Jaehyouk; Kang, Yesung; Kim, YoungminARTICLE450
201709Analysis and reduction of the voltage noise of multi-layer 3D IC with multi-paired power delivery networkKim, Seungwon; Kim, YoungminARTICLE24
201412Comprehensive Performance Analysis of Interconnect Variation by double and triple patterning lithography processesKim, Youngmin; Lee, Jaemin; Ryu, MyunghwanARTICLE306
2015-02Cryptography Engine Design for IEEE 1609.2 WAVE Secure Vehicle Communication using FPGAKim, Youngmin; Jeong, ChanbokMaster's thesis1182
201111Diffusion-rounded CMOS for improving both I-on and I-off characteristicsRyu, Myunghwan; Nguyen, Hung Viet; Kim, YoungminARTICLE307
201508Impacts of Trapezoidal Fin of 20-nm Double-Gate FinFET on the Electrical Characteristics of CircuitsRyu, Myunghwan; Kim, YoungminARTICLE178
201709In Situ Electrochemical Activation of Atomic Layer Deposition Coated MoS2 Basal Planes for Efficient Hydrogen Evolution ReactionKim, Youngmin; Jackson, David H. K.; Lee, Daewon; Choi, Min; Kim, Tae-Wan; Jeong, Soon-Yong; Chae, Ho-Jeong; Kim, Hyun Woo; Park, Noejung; Chang, Hyunju; Kuech, Thomas F.; Kim, Hyung JuARTICLE8
201305Intra-gate length biasing for leakage optimization in 45nm technology nodeKang Yesung; Kim, YoungminARTICLE328
201606Novel adaptive power-gating strategy and tapered TSV structure in multilayer 3D ICKim, Seung Won; Kang, Seokhyeong; Han, Ki Jin; Kim, YoungminARTICLE309
2012-08Novel IC designs with 32 nm Independent-Gate FinFETKim, Youngmin; Nguyen, Hung VietMaster's thesis400
201506On-chip interconnect boosting technique by using of 10-nm double gate-all-around (DGAA) transistorLee, Jaemin; Ryu, Myunghwan; Kim, YoungminARTICLE262
201601Optimal inverter logic gate using 10-nm double gate-all-around (DGAA) transistor with asymmetric channel widthRyu, Myunghwan; Bien, Franklin; Kim, YoungminARTICLE191
200709Self-compensating design for reduction of timing and leakage sensitivity to systematic pattern-dependent variationGupta, Puneet; Kahng, Andrew B.; Kim, Youngmin; Sylvester, DennisARTICLE270
2013-08Simple and accurate modeling of the 3D structural variations in FinFETsKim, Youngmin; Kim, DonghuMaster's thesis502
200908Simple and Accurate Models for Capacitance Considering Floating Metal Fill InsertionKim, Youngmin; Petranovic, D.; Sylvester, D.ARTICLE235
2013Trapezoidal approximation for on-current modeling of 45-nm non-rectilinear gate shapeRyu, Myunghwan; Kim, YoungminARTICLE350
201212TSV Geometrical Variations and Optimization Metric with Repeaters for 3D ICNguyen, Hung Viet ; Ryu, Myunghwan; Kim, YoungminARTICLE281
Showing results 1 to 20 of 21

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