File Download

There are no files associated with this item.

  • Find it @ UNIST can give you direct access to the published full text of this article. (UNISTARs only)
Related Researcher

윤희인

Yoon, Heein
Advanced Circuits and Electronics Lab.
Read More

Views & Downloads

Detailed Information

Cited time in webofscience Cited time in scopus
Metadata Downloads

A Framework of Automated LC-VCO Design with Physical Layout Based on Reinforcement Learning

Author(s)
Kim, SungjinLee, HyunsooHong, SeongminYoon, HeeinSong, Taigon
Issued Date
2026-03
DOI
10.1109/TCAD.2026.3680789
URI
https://scholarworks.unist.ac.kr/handle/201301/91645
Fulltext
https://ieeexplore.ieee.org/abstract/document/11474599
Citation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Abstract
Artificial Intelligence (AI) has been increasingly utilized across various fields, including communications, healthcare, and Computer-Aided Design (CAD). However, AI has shown relatively limited advances in analog and RF circuit design, which are critical for modern communication systems such as 5G due to their higher complexity and nonlinear characteristics. For example, the Inductor-Capacitor Voltage-Controlled Oscillator (LC-VCO) is a crucial component in frequency synthesizers, determining the performance of RF systems, including high data transmission rates and wide bandwidth. In fact, LC-VCO design is challenging due to the high parameter variability and complex interactions between design variables, making it challenging to optimize parameters to meet target specifications. Thus, this study proposes a comprehensive LC-VCO design methodology compatible across multiple process nodes and supports optimization down to the layout level. We use Reinforcement Learning (RL) to navigate the nonlinear design space efficiently for schematic optimization and apply an algorithm from Gradient Descent to optimize the design at the physical layout level. We highlight that the versatility of our methodology is demonstrated by producing optimized Figures of Merit (FoM) across various technology nodes and frequency ranges, showcasing its potential as a universal design tool accessible to all users.
Publisher
IEEE
ISSN
0278-0070

qrcode

Items in Repository are protected by copyright, with all rights reserved, unless otherwise indicated.