Heterogeneous 3D CFET with Ge Nanosheet Channel

Abstract

Recently, complementary field-effect transistors (CFETs) have been seriously studied for next-generation device architectures to further improve PPA (power, performance, and area). However, there are still many challenges including process integration and structure optimization, decisions on implementation schemes (monolithic or sequential), etc. At the transistor level, unbalanced transport between n- and p-FET would be one of the most critical issues because CFETs inherently require the same width between n- and p-FETs. Here, we will discuss the opportunity of heterogeneous or hybrid channel design to mitigate these issues and its process flexibility to realize CFETs.