Heterogeneous 3D CFET with Hybrid Channel Configuration

Abstract

Complementary field-effect transistors (CFETs) have been seriously studied for next-generation device architectures to improve PPA (power, performance, and area). However, many challenges remain, including process integration, structure optimization, implementation schemes (monolithic/sequential), etc. At the transistor level, unbalanced transport between n- and p-FET would be one of the most critical issues because CFETs inherently require the same width both for n- and p-FETs. Furthermore, new parameters such as spacing length between top and bottom FETs have emerged. Here, we discuss the opportunity for heterogeneous channel design to mitigate these issues.