Transfer-free Fabrication of All-2D Metal-Semiconductor Junctions for High-Performance 2D Electronics

Abstract

Modern electronics have advanced by continuous down-scaling over the past decades, leading to high integration density and remarkable improvements in speed, efficiency, and functionality. However, conventional bulk semiconductor devices are approaching their quantum limits due to severe short-channel effects (SCEs) and surface scattering, posing a major bottleneck for further scaling. These challenges underscore the urgent need for alternative materials, prompting the development of semiconducting two-dimensional (2D) transition metal dichalcogenides (TMDs) as channels for field-effect transistors (FETs). With atomically thin layered structure and dangling bond-free surfaces, 2D TMDs offer strong electrostatic control and superior carrier transport, enabling reliable operation even at the atomic scale. Nevertheless, establishing high-quality metal contacts on surface 2D TMDs remains a critical challenge owing to their ultrathin body and delicate lattices. Van der Waals (vdW) contacts, particularly using 2D semimetals leverage the intrinsic vdW gap to form atomically sharp metal–semiconductor junctions (MSJs) while preserving the structural integrity of the 2D channel. However, the fabrication of 2D semimetals often relies on transfer-based approaches to avoid fabrication-induced damage, including metal atom bombardment during precursor deposition and thermal damage from high-temperature chemical vapor deposition (CVD, >500 °C). These processes can induce interfacial defects in the underlying 2D channel, ultimately degrading device performance and reliability.

In this thesis, we report a low-temperature (350 °C) synthesis method of 2D semimetals and transfer-free fabrication into all-2D MSJ with clean interfaces. First, by employing all-solid-state chalcogen/transition metal stacks (CTS; Te/Mo, Te/Pt, and Se/Pt), we synthesized diverse 2D semimetals, including 1T′-MoTe₂, 1T-PtTe₂, and 1T-PtSe₂ upon annealing at 350 °C (Chapter 2). We investigated the conversion of CTS into 2D semimetals using Raman spectroscopy and XPS analysis. Furthermore, the CTS-synthesized 2D semimetals show wafer-scale compatibility and appropriate electrical properties, including sheet resistance (RSH) and work function. To investigate the clean MSJ enabled by the CTS approach, we fabricated 2H-MoTe₂ devices in which CTS-synthesized 2D semimetals served as source and drain electrodes (Chapter 3). Te/Mo CTS stacks were deposited on 2H-MoTe₂ and converted into 1T′-MoTe₂ through annealing at 350 °C. In this process, the Te layer acts simultaneously as an encapsulation layer and chalcogen precursor, effectively protecting the underlying 2H-MoTe₂ surface during fabrication process and enabling the formation of clean 2D/2D heterojunctions. The protective effect was further validated by comparing bare 2H-MoTe₂ with 2H-MoTe₂/Te heterostructures, and cross-sectional TEM analysis confirmed the formation of atomically sharp interfaces and clean all-2D MSJs after annealing. In addition, first-principles calculations indicate that Te and Se atoms can migrate toward Te vacancies in the underlying 2H-MoTe2 through relatively low energy barriers (Eb ≈ 0.42–0.56 eV), suggesting a mild chalcogen-healing effect that further contributes to interface preservation. The final section explores the electrical characteristics of CTS-driven all-2D MSJ FET arrays (Chapter 4). We integrated diverse CTS-synthesized 2D semimetals, including 1T′-MoTe₂, 1T-PtTe₂, and 1T-PtSe₂, to form all-2D MSJ heterojunctions compatible with the 2H-MoTe₂ channel. The resulting devices exhibit outstanding electrical performance, including efficient charge injection, high field-effect hole mobility (μₕ ≈ 24 cm²/V·s) with low device-to-device variation (3.7%), and ideal Schottky barrier heights, with the lowest value of 31 meV achieved for the 1T′/2H-MoTe₂ MSJ. Other CTS-derived 2D electrodes likewise showed favorable band alignment and comparable electrical properties, demonstrating the generality and robustness of the CTS integration strategy. Collectively, these results establish CTS as a scalable, CMOS-compatible method for realizing high-performance 2D metallic contacts.