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Small Molecular Inhibitor-Assisted Area-Selective ALD Enabling Bottomless Ru/ZnO Bilayer Barrier Integration for Scaled Cu Interconnects

Author(s)
Kim, Minwoo
Advisor
Kim, Soo-Hyun
Issued Date
2026-02
URI
https://scholarworks.unist.ac.kr/handle/201301/91081 http://unist.dcollection.net/common/orgView/200000965795
Abstract
Interconnect resistance has emerged as a critical bottleneck in advanced integrated circuits, driven by the increasing volume fraction of high-resistivity barrier and liner layers in Cu interconnects. Conventional TaN barriers require high vacuum deposition temperatures (>250 °C) or plasma-enhanced atomic layer deposition (PE-ALD), conditions incompatible with inhibitor-assisted area-selective ALD (AS-ALD). Here, we introduce a bottomless barrier architecture strategy that selectively deposits barrier material on the via sidewalls while leaving the Cu bottom surface exposed, significantly reducing contact resistance. Phenylethyl mercaptan (PEM) is employed as a inhibitor selectively adsorbed on Cu, leveraging strong Cu–S chemisorption and π–π interactions to form a densely packed layer with superior blocking performance. ZnO is chosen as the barrier material due to its low-temperature ALD capability (<150 °C), strong interfacial adhesion through ZnSiO4 formation, and effective suppression of Cu diffusion. The AS-ALD process exhibited robust selectivity, maintaining approximately 90% selectivity until 9 nm of ZnO was deposited on SiO₂, confirming stable inhibition performance even at relatively large film thicknesses. ALD-Ru is subsequently deposited as a liner and seed layer, providing low resistivity, oxidation resistance, and enhanced Cu crystallinity. The resulting Ru/ZnO bilayer on SiO₂ sidewalls and the Ru layer on the Cu bottom surface are integrated into dual-damascene patterns prior to Cu filling. This approach demonstrates a scalable, small-molecular PEM inhibitor-assisted AS-ALD process for advanced interconnects, enabling reduced via resistance and improved reliability to overcome the limitations of modern-day interconnects.
Publisher
Ulsan National Institute of Science and Technology
Degree
Master
Major
Graduate School of Semiconductor Materials and Devices Engineering Semiconductor Materials and Devices Engineering

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