Scaled Oxide Semiconductor Vertical Channel Transistors with Enhanced Channel-Sidewall Interfaces for 2T0C Gain Cell Memory

Abstract

Monolithically stacked 2T0C gain-cell memory based on amorphous oxide semiconductor (AOS) vertical-channel transistors (VCTs), integrated directly atop processor logic, has emerged as a promising high-density embedded dynamic random-access memory (eDRAM) solution for memory-centric computing systems. Unlike planar transistors, however, VCTs inherently require a hole-etching process to form vertical channels, making the condition of the etched sidewall a critical factor that directly governs channel characteristics. Despite this importance, the role of sidewall condition in VCTs, as well as the impact of the sidewall material properties on device performance, has not yet been investigated. In this study, we identify transfer-characteristic degradation induced by hole-diameter (DH) scaling in oxide-semiconductor VCTs, which is absent in planar devices. We further experimentally demonstrate that the barrier limiting DH scaling in OS-VCTs originates from sidewall degradation induced during the hole-etching process. By-products and ionic residues generated during etching contaminate the sidewalls, resulting in increased off-state leakage current, elevated contact resistance, and the formation of sub-gap states in the channel. To overcome this fundamental scaling limitation, we introduce a dedicated post- etch cleaning process that effectively removes etch-induced residues, achieving a three-order- of-magnitude improvement in both drain current (ID) and contact resistance (RC). Furthermore, the etched sidewall directly forms the interface with the channel, we propose a SiN/SiO2/SiN interlayer stack to ensure long-term stabilization of the sidewall–channel interface. The oxygen-supplying SiO2 layer stabilizes oxygen vacancies through annealing while enhancing percolation efficiency, whereas the surrounding SiN layers effectively suppress electrode oxidation. As a result, a record-high drain current density of 436 μA μm⁻1 is achieved in aggressively scaled VCTs, along with improved bias stability. Overall, this work demonstrates that high performance, in terms of drive current and bias stability, can be achieved in scaled VCTs through sidewall cleaning and interface engineering, thereby validating the potential of monolithically integrated gain-cell memory as a future eDRAM technology.