Tunneling-Based Ternary CMOS Technology with PVT Variation Tolerance for High-Density and Low-Power Memory Application

Abstract

In the data-centric era, static random access memory (SRAM) plays a vital role in advancing system- on-chip (SoC) design, from energy-efficient AI computing to low-power edge devices. The ongoing demand for high-capacity on-chip memory is driving transistor scaling toward 4-nm FinFET and 2-nm nanosheet technologies. Despite these efforts, the process, voltage, and temperature (PVT) variations are exacerbated in 3D CMOS architectures by aggressive gate and interconnect pitch scaling, along with reduced heat-dissipation paths due to channel segmentation. As a result, recent 5-/3-/2-nm nodes have delivered only ∼10% bit-density enhancement, while the minimum supply voltage has remained nearly constant from 28-nm down to 2-nm node. Conventional drift–diffusion based CMOS, which imposes excessive electric fields in the channel region, cannot effectively address these integration- and power-density challenges. To overcome these issues, this thesis presents a PVT variation-tolerant tunneling-based ternary CMOS (T-CMOS) technology with scalability to 3D device architectures and a macro-level ternary on-chip memory implementation. In a commercial 28-nm process—featuring a shallower source/drain (S/D) junction depth than legacy planar nodes—the halo implant is engineered to form a locally-confined bulk tunnel junction near the S/D extension, enabling T-CMOS operation. This well-localized halo profile improves the leakage scalability and enlarges the design window, allowing various ternary functions from the nominal 1.0 V down to ultra-scaled VDD of 0.3 V. Thus, the proposed 28-nm halo-based ternary SRAM cell (TritCellTM) exhibits the best FoM (cell area × leakage power), even ∼5× better than 14-nm FinFET bitcell. To mitigate the increased threshold-voltage variation (σVT) in 28-nm T-CMOS induced by the highly doped tunnel junction, S/D underlap profile is adopted. Lowering S/D doping concentration by 80% nearly doubles the effective channel length, leading to 16% reduction in σVT. Leveraging a bulk tunnel junction physically decoupled from gate-edge roughness and metal-grain fluctuations, TritCellTM at nominal VDD achieves a 15% larger noise margin than bitcell in retention mode. In addition, the off- leakage temperature sensitivity is drastically reduced by 94% across −40 to 125◦C. Moreover, the proposed S/D underlap profile, combined with structural separation between the tunnel junction and the channel in Fin/GAA architectures, enables a more robust 3D T-CMOS implementation. Building on this variation-tolerant device platform, mega-bit (Mb) scale 28-nm T-SRAM macro is demonstrated. By leveraging 1.5-bit/cell storage with binary I/O compatible interface, the proposed T-SRAM boosts macro bit-density by up to +33.4% when configured as a 16-Mb block. Furthermore, a tunneling-based ternary latch that decouples cell leakage from the read-access current enables 55% dynamic power reduction across worst-case PVT corners, compared with the baseline bitcell. These bit-density and access-energy benefits are expected to further improve in the 3D Fin/GAA technologies, projected to reach 38.5 Mb/mm2 macro density and 0.014 pJ/bit access energy, outperforming conventional 2-nm nanosheet SRAM. Therefore, the proposed PVT variation-tolerant T-CMOS platform provides a scalable on-chip memory solution for next-generation SoCs.