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Park, Heechun
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dc.citation.endPage 6445 -
dc.citation.number 8 -
dc.citation.startPage 6407 -
dc.citation.title ACS NANO -
dc.citation.volume 20 -
dc.contributor.author Jung, Haksoon -
dc.contributor.author Choi, Joonghoon -
dc.contributor.author Baek, Seunghun -
dc.contributor.author Shin, Bong Gyu -
dc.contributor.author Song, Young Jae -
dc.contributor.author Jung, Hanggyo -
dc.contributor.author Kim, JoHyeon -
dc.contributor.author Jeon, Jongwook -
dc.contributor.author Kim, Gyumin -
dc.contributor.author Park, Heechun -
dc.contributor.author Lee, Yeonjoo -
dc.contributor.author Yoo, Jinkyoung -
dc.contributor.author Lee, Jae-Hyun -
dc.contributor.author Kim, Hyungwoo -
dc.contributor.author Kang, Kibum -
dc.contributor.author Jeong, Jaeyong -
dc.contributor.author Kim, Sang Hyeon -
dc.contributor.author Bae, Joohan -
dc.contributor.author Kim, Chang Soo -
dc.contributor.author Yang, Won Kwang -
dc.contributor.author Lee, Sungjoo -
dc.contributor.author Kwon, Jiwook -
dc.contributor.author Kim, Byung-Sung -
dc.contributor.author Han, Jae-Hoon -
dc.contributor.author Kim, Hyung-Jun -
dc.contributor.author Yoon, Hoon Hahn -
dc.contributor.author Kwon, Jimin -
dc.contributor.author Hong, Young Joon -
dc.date.accessioned 2026-03-24T17:35:08Z -
dc.date.available 2026-03-24T17:35:08Z -
dc.date.created 2026-03-09 -
dc.date.issued 2026-03 -
dc.description.abstract The emergence of ultralarge-scale hardware systems for artificial intelligence is driving demand for high-performance heterogeneous integration. At the heart of these systems lies the maximization of computational capability through high data bandwidth, necessitating interconnects that either increase the number of links between tiers and chips or enhance the data transfer rate of each link. Monolithic three-dimensional (M3D) integration, particularly with two-dimensional (2D) materials, offers ultradense intertier vias and multifunctional devices within back-end-of-line-compatible processes, enabling compact vertical stacking of logic and memory. A critical challenge in this architecture is thermal management, requiring cross-layer electro-thermal analysis and codesign with integrated power regulation. In parallel, photonic integrated circuits provide low-latency, energy-efficient interchip communication by overcoming the traditional bandwidth limitation imposed by electrical signal loss, and their advantages become increasingly significant as the communication distance increases. Emerging concepts, including spectrally tunable 2D photodetectors and vertically stacked microlight-emitting-diode-photodiode transceivers, further enhance scalability by eliminating reliance on external lasers. This Review article highlights the convergence of M3D integration, 2D materials, and photonic interconnects, while outlining challenges of material compatibility, process scalability, and system-level codesign that must be addressed to realize a unified framework for next-generation computing and communication systems beyond conventional Si scaling. -
dc.identifier.bibliographicCitation ACS NANO, v.20, no.8, pp.6407 - 6445 -
dc.identifier.doi 10.1021/acsnano.5c15601 -
dc.identifier.issn 1936-0851 -
dc.identifier.uri https://scholarworks.unist.ac.kr/handle/201301/90795 -
dc.identifier.wosid 001694431500001 -
dc.language 영어 -
dc.publisher AMER CHEMICAL SOC -
dc.title Advances and Future Challenges in Monolithic 3D Integrated Logic, Power, and Optoelectronics Technologies for Tightly Interconnected Intelligent Systems -
dc.type Article -
dc.description.isOpenAccess FALSE -
dc.relation.journalWebOfScienceCategory Chemistry, Multidisciplinary; Chemistry, Physical; Nanoscience & Nanotechnology; Materials Science, Multidisciplinary -
dc.relation.journalResearchArea Chemistry; Science & Technology - Other Topics; Materials Science -
dc.type.docType Review -
dc.description.journalRegisteredClass scie -
dc.description.journalRegisteredClass scopus -
dc.subject.keywordAuthor advanced packaging -
dc.subject.keywordAuthor copackaged optics -
dc.subject.keywordAuthor optical interconnects -
dc.subject.keywordAuthor photonicintegrated circuits -
dc.subject.keywordAuthor design-technology co-optimization -
dc.subject.keywordAuthor power delivery network -
dc.subject.keywordAuthor thermal management -
dc.subject.keywordAuthor 2D materials -
dc.subject.keywordAuthor microlight-emitting diodes -
dc.subject.keywordAuthor heterogeneously integratedmonolithic 3D -
dc.subject.keywordPlus SILICON INTERPOSER -
dc.subject.keywordPlus LIGHT-EMITTING-DIODES -
dc.subject.keywordPlus 2-DIMENSIONAL MATERIALS -
dc.subject.keywordPlus ANALYTICAL PLACEMENT -
dc.subject.keywordPlus DESIGN METHODOLOGY -
dc.subject.keywordPlus MOS2 TRANSISTORS -
dc.subject.keywordPlus MICRO-LEDS -
dc.subject.keywordPlus PERFORMANCE -
dc.subject.keywordPlus PHOTONICS -
dc.subject.keywordPlus ATOMIC LAYER DEPOSITION -

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