Enhanced Fermi-level Pinning Driven by Graphene Interlayer in Metal/4H-SiC Junction

Abstract

The Fermi-level pinning of metal/semiconductor junction is a phenomenon that describes the Schottky barrier as being independent of metal work-function. It has been reported that the metal/Si junction with a graphene interlayer preserves the strong Fermi-level pinning observed in the junction with no graphene interlayer. The influences of graphene interlayer on the Fermi-level pinning have been explored also for other semiconductors such as GaAs and Ge. In this work, we report the enhancement of Fermi-level pinning at metal/graphene/4H-SiC junctions made of monolayer or bilayer graphene. Here, it is noted that the Fermi-level pinning of metal/4H-SiC junction without a graphene interlayer is relatively weak. The metal/graphene/4H-SiC junction was fabricated by first transferring a CVD-grown graphene layer onto a highly n-type doped 4H-SiC substrate with semi-dry transfer method and then depositing circular metal( Al, Ni, Pt) electrodes onto the transferred graphene layer through a metal shadow mask. The barrier heights were extracted from current-voltage (I-V) and capacitance-voltage (C-V) curves. The pinning factor S of metal/graphene/4H-SiC junction was found to decrease significantly for both monolayer and bilayer graphene compared with the metal/4H-SiC junction, directly implying that the Fermi-level pinning became stronger. This enhancement of Fermi-level pinning is considered to be driven by the Dirac-semimetal nature of graphene. More concretely, the Dirac point of the band structure of graphene can take a role of the charge neutral level in the interface dipole layer model for the Fermi-level pinning.