Superconducting Flip-Chip Bonding for Multi-Tier Quantum Processors

Abstract

The scalability of superconducting qubit system on a 2D plane is strongly limited due to the relatively large sizes, at least several micrometers, of qubit themselves and other drive/read-out circuit elements(feedlines, resonators). The standard and efficient strategy to overcome this limitation of 2D planar architecture is to fabricate the drive/read-out circuitryon a separate chip(control chip) and stack it vertically with a qubit-only chip to form a multi-tier or 3D-integrated structure. The key technological ingredients of multi-tier architecture are superconducting bump flip-chip bonding and through-Si-via(TSV) interconnect line [1]. Especially, the superconducting bump flip-chip bonding is the must-have technology for realizing the 3D-integrated processors. In this talk, the overview for the multi-tier superconducting quantum processors will be given together with the domestic and international status of adopting it to the actual processor fabrication [2,3]. Also, our recent works of fabricating a two-tier superconducting quantum processor by stacking a twenty-qubit transmon chip on top of a control chip using the two-layersuperconducting bumps will be introduced in terms of the fabrication procedures and operational characteristics of qubits.

Keywords: Superconducting qubit, Superconducting quantum processor, Multi-tier architecture, Superconducting bump, Flip-chip bonding, TSV, Superconducting resonator

[1] D. Rosenberg et al., “3D integrated superconducting qubits”, npj Quantum Information 42 (2017)

[2] S. Kosen et al., “Building blocks of a flip-chip integrated superconducting quantum processor”, Quantum Science and Technology 7, 035018 (2022)

[3] G. Norris et al., “Improved parameter targeting in 3D-integrated superconducting circuits through a polymer spacer process”, EPJ Quantum Technology 11, 5 (2024)