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- Lee, Jongeun
- Intelligent Computing and Codesign Lab.
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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.assignee | 울산과학기술원 / 인하대학교 / 성균관대학교 산학협력단 | - |
| dc.contributor.author | 이종은 | - |
| dc.contributor.author | 홍민욱 | - |
| dc.contributor.author | 이수길 | - |
| dc.contributor.author | 권기원 | - |
| dc.contributor.author | 김형진 | - |
| dc.contributor.author | 윤상욱 | - |
| dc.contributor.author | 박진우 | - |
| dc.contributor.author | 유민상 | - |
| dc.date.accessioned | 2025-12-16T14:35:31Z | - |
| dc.date.application | 2024-06-11 | - |
| dc.date.available | 2025-12-16T14:35:31Z | - |
| dc.date.registration | 2025-10-29 | - |
| dc.identifier.patentApplicationNumber | 10-2024-0075529 | - |
| dc.identifier.patentRegistrationNumber | 10-2880189 | - |
| dc.identifier.uri | https://scholarworks.unist.ac.kr/handle/201301/89083 | - |
| dc.title | 패시브 저항성 메모리의 연산 에러를 방지하는 장치 및 방법 | - |
| dc.type | Patent | - |
| dc.publisher.country | KO | - |
| dc.type.iprs | 특허 | - |
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