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BielawskiChristopher W

Bielawski, Christopher W.
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dc.citation.number 19 -
dc.citation.startPage e00469 -
dc.citation.title ADVANCED ELECTRONIC MATERIALS -
dc.citation.volume 11 -
dc.contributor.author Han, Sangoh -
dc.contributor.author Jung, Dohwan -
dc.contributor.author Bae, Jonghyun -
dc.contributor.author Chae, Juyoung -
dc.contributor.author Bong, Haekyun -
dc.contributor.author Sultane, Prakash R. -
dc.contributor.author Bielawski, Christopher W. -
dc.contributor.author Oh, Jungwoo -
dc.date.accessioned 2025-11-26T09:14:13Z -
dc.date.available 2025-11-26T09:14:13Z -
dc.date.created 2025-11-11 -
dc.date.issued 2025-10 -
dc.description.abstract Beryllium oxide (BeO) has exceptionally high thermal conductivity (330 W m(-1)K-1), a large bandgap energy, and a high dielectric constant, making it an optimal dielectric for high-power devices. However, its direct application on 4H-SiC is hindered by interfacial carbon-cluster formation during high-temperature annealing, primarily due to the decomposition of 4H-SiC. In this study, a SiO2 interlayer is introduced between BeO and 4H-SiC using plasma-enhanced chemical-vapor deposition to address these challenges. Electrical measurements reveal that the BeO/SiO2/4H-SiC stack exhibits a reduced leakage-current density, an enhanced breakdown field (>7.5 MV cm(-1)), and a smaller capacitance-voltage hysteresis compared with direct BeO deposition owing to reduced interface defects. Band-alignment analysis shows an increased conduction-band offset between BeO/4H-SiC, potentially contributing to improved carrier confinement. The interface trap density (Dit) is reduced by two orders of magnitude, indicating an improved interface quality owing to the presence of the SiO2 interlayer. The SiO2 interlayer significantly improves interface quality, reduces leakage current, and enhances the breakdown field of the BeO/4H-SiC system. These results suggest that interfacial engineering using a SiO2 interlayer can be an effective approach for improving the electrical reliability of high-temperature dielectric stacks on 4H-SiC. -
dc.identifier.bibliographicCitation ADVANCED ELECTRONIC MATERIALS, v.11, no.19, pp.e00469 -
dc.identifier.doi 10.1002/aelm.202500469 -
dc.identifier.issn 2199-160X -
dc.identifier.scopusid 2-s2.0-105020436711 -
dc.identifier.uri https://scholarworks.unist.ac.kr/handle/201301/88452 -
dc.identifier.wosid 001603633200001 -
dc.language 영어 -
dc.publisher WILEY -
dc.title Enhancing Electrical and Interfacial Properties of BeO/4H-SiC Structures with SiO2 Interlayer -
dc.type Article -
dc.description.isOpenAccess TRUE -
dc.relation.journalWebOfScienceCategory Nanoscience & Nanotechnology; Materials Science, Multidisciplinary; Physics, Applied -
dc.relation.journalResearchArea Science & Technology - Other Topics; Materials Science; Physics -
dc.type.docType Article; Early Access -
dc.description.journalRegisteredClass scie -
dc.description.journalRegisteredClass scopus -
dc.subject.keywordAuthor interface defect -
dc.subject.keywordAuthor silicon carbide -
dc.subject.keywordAuthor atomic-layer deposition -
dc.subject.keywordAuthor band alignment -
dc.subject.keywordAuthor beryllium oxide -
dc.subject.keywordPlus PRECISE DETERMINATION -
dc.subject.keywordPlus THERMAL-CONDUCTIVITY -
dc.subject.keywordPlus 4H-SIC MOSFETS -
dc.subject.keywordPlus MOBILITY -
dc.subject.keywordPlus OXIDE -
dc.subject.keywordPlus BEO -

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