This article presents a CMOS flash light detection and ranging (LiDAR) sensor featuring an analog-assisted in-pixel zoom histogramming time-to-digital converter (hTDC) to pave the way for realizing an area-and energy-efficient architecture. The proposed hTDC substitutes digital counters and logic in the timing generator (TG) in the previous hTDC with analog counterparts comprising a time-to-analog converter (TAC) and a self-referenced successive approximation register analog-to-digital converter (SAR ADC). It supports the two-step zoom hTDC functionality based on the SA-hTDC for the coarse step and the indirect time-of-flight (iToF) technique for the fine step. The proposed architecture minimizes the need for high-frequency clocks, resulting in an impressively low pixel power consumption of 3.1 mu W per pixel. In addition, by placing the capacitors underneath the SPAD device, the pixel pitch is scaled down to 35 mu m. The self-referenced SAR ADC mitigates PVT variations in the analog TG and suppresses the pixel-to-pixel nonuniformities in the conversion slope of the TAC. The D-latches in the depth memory are repurposed to store and read the 4-b coarse ToF sequentially and the 10-b digital output of the single-slope (SS) ADC from the fine operation. The prototype LiDAR sensor with a 160 x 120 pixel array was fabricated in a 0.11- mu m CMOS image sensor (CIS) process. The coarse TDC offers a resolution of 1.5 m, providing a detection range of up to 24 m. The coarse and fine TDC measures a depth accuracy of 2.9 cm and precision of 3.5 cm, respectively, within a range of 3-4.4 m.