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Jeong, Hongsik
Future Semiconductor Technology Lab.
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An Optimized Device Structure with a Highly Stable Process Using Ferroelectric Memory in 3D NAND Flash Memory Applications

Choi, SeonjunKang, MyounggonJeong, HongsikKim, YuriSong, Yun-heub
Issued Date
ELECTRONICS, v.13, no.5, pp.889
In this paper, we propose an optimized device structure with a highly stable process that addresses threshold voltage shift issues in the String-Select-Line (SSL) and Ground-Select-Line (GSL) gates using ferroelectric memory in 3D NAND flash memory applications. The proposed device utilizes nickel (Ni) instead of tungsten (W) for the GSL and SSL gates, enabling optimized polarization properties during the annealing process and leveraging the disparity in thermal expansion coefficients. Notably, the difference in thermal expansion coefficient from tungsten (W), employed in other Word Line (WL) gates, allows effective control over polarization properties. To validate the proposed structure, we fabricated and measured a Metal-Ferroelectric-Insulator-Silicon (MFIS) capacitor utilizing Hafnium-Zirconium Oxide (HZO) material. The measurement results indicate that a change in the upper metal layer results in a more than fivefold increase in the variance of polarization characteristics between the WL gates (responsible for the memory function) and the SSL and GSL gates dedicated to channel control. In addition, process simulation was conducted using the same device structure, confirming the application of tensile stress to the HZO thin film in the case of a W electrode and compressive stress in the case of a Ni electrode. Furthermore, applying this controlled polarization characteristic parameter to the 3D NAND flash memory structure revealed a reduction in the threshold voltage shift of the control gate from a previous change of 2.6 V or more to 0.05 V, facilitating stable control.
Keyword (Author)
3D NANDcharge trap flash (CTF)ferroelectricstress


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