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- Park, Heechun
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| DC Field | Value | Language |
|---|---|---|
| dc.citation.conferencePlace | US | - |
| dc.citation.title | IEEE International Symposium on Quality Electronic Design (ISQED), 2024 | - |
| dc.contributor.author | Yoon, Junghyun | - |
| dc.contributor.author | Park, Heechun | - |
| dc.date.accessioned | 2024-03-15T09:35:08Z | - |
| dc.date.available | 2024-03-15T09:35:08Z | - |
| dc.date.created | 2024-03-15 | - |
| dc.date.issued | 2024-04-03 | - |
| dc.identifier.bibliographicCitation | IEEE International Symposium on Quality Electronic Design (ISQED), 2024 | - |
| dc.identifier.uri | https://scholarworks.unist.ac.kr/handle/201301/81658 | - |
| dc.publisher | IEEE | - |
| dc.title | Design-Technology Co-Optimization with Standard Cell Layout Generator for Pin Configurations | - |
| dc.type | Conference Paper | - |
| dc.date.conferenceDate | 2024-04-03 | - |
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