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Park, Heechun
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dc.citation.endPage 511 -
dc.citation.number 3 -
dc.citation.startPage 499 -
dc.citation.title IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS -
dc.citation.volume 29 -
dc.contributor.author Kim, Taewhan -
dc.contributor.author Park , Heechun -
dc.date.accessioned 2024-03-13T15:35:09Z -
dc.date.available 2024-03-13T15:35:09Z -
dc.date.created 2024-03-13 -
dc.date.issued 2021-03 -
dc.description.abstract It is generally known that a considerable portion of flip-flops in circuits is occupied by the ones with mux-feedback loop (called self-loop), which is the critical (inherently unavoidable) bottleneck in minimizing total (always-on) storage size for the allocation of nonuniform multibits for retaining flip-flop states in power gated circuits. This is because it is necessary to replace every self-loop flip-flop with a distinct retention flip-flop with at least one-bit storage for retaining its state since there is no clue where the flip-flop state, when waking up, comes from, i.e., from the mux-feedback loop or from the driving flip-flops other than itself. This work breaks this bottleneck by safely treating a large portion of the self-loop flip-flops as if they were the same as the flip-flops with no self-loop. Specifically, we design a novel mechanism of steady-state monitoring, operating for a few cycles just before sleeping, on a partial set of self-loop flip-flops, by which the expensive state retention storage is never be needed for the monitored flip-flops, contributing to a significant saving on the total size of the always-on state retention storage for power gating. Through experiments with benchmark circuits, it is shown that our proposed method is able to reduce the total number of retention bits by 27.12% on average when at most 2-bit retention flip-flop is used, saving standby power by 19.41% compared with the state-of-the-art conventional method. -
dc.identifier.bibliographicCitation IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.29, no.3, pp.499 - 511 -
dc.identifier.doi 10.1109/TVLSI.2020.3047056 -
dc.identifier.issn 1063-8210 -
dc.identifier.scopusid 2-s2.0-85099724161 -
dc.identifier.uri https://scholarworks.unist.ac.kr/handle/201301/81626 -
dc.identifier.wosid 000622096700005 -
dc.language 영어 -
dc.publisher IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC -
dc.title Allocation of Always-On State Retention Storage for Power Gated Circuits-Steady-State- Driven Approach -
dc.type Article -
dc.description.isOpenAccess FALSE -
dc.relation.journalWebOfScienceCategory Computer Science, Hardware & Architecture; Engineering, Electrical & Electronic -
dc.relation.journalResearchArea Computer Science; Engineering -
dc.type.docType Article -
dc.description.journalRegisteredClass scie -
dc.description.journalRegisteredClass scopus -
dc.subject.keywordAuthor Clocks -
dc.subject.keywordAuthor Resource management -
dc.subject.keywordAuthor Logic gates -
dc.subject.keywordAuthor Monitoring -
dc.subject.keywordAuthor Integrated circuit modeling -
dc.subject.keywordAuthor Steady-state -
dc.subject.keywordAuthor Hardware design languages -
dc.subject.keywordAuthor Allocation -
dc.subject.keywordAuthor leakage power -
dc.subject.keywordAuthor logic design -
dc.subject.keywordAuthor optimization -
dc.subject.keywordAuthor power gating -
dc.subject.keywordAuthor state retention -

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