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DC Field | Value | Language |
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dc.citation.endPage | 279 | - |
dc.citation.number | 2 | - |
dc.citation.startPage | 266 | - |
dc.citation.title | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | - |
dc.citation.volume | 34 | - |
dc.contributor.author | Park, Heechun | - |
dc.contributor.author | Kim, Taewhan | - |
dc.date.accessioned | 2024-03-13T15:05:09Z | - |
dc.date.available | 2024-03-13T15:05:09Z | - |
dc.date.created | 2024-03-13 | - |
dc.date.issued | 2015-02 | - |
dc.description.abstract | In through-silicon-via (TSV) based 3-D integrated chips (ICs), synthesizing 3-D clock tree is one of the most challenging tasks. Since the clock signal is delivered to clock sinks (e.g., latches, flip-flops) through TSVs, any fault on a TSV in the clock tree may cause a chip failure. Therefore, ensuring the reliability of clock TSVs in 3-D ICs is highly important. To cope with clock TSV reliability problem effectively, we propose a new circuit cell called slew-controlled TSV fault-tolerant unit (SC-TFU) which overcomes the limited capability of the conventional TFUs and propose a full solution to the problem of designing and synthesizing 3-D TSV fault-tolerant clock tree based on SC-TFUs. Precisely, for a presynthesized 3-D clock tree, we solve the problem in three steps: 1) performing a comprehensive TSV pairing algorithm to maximally allocate SC-TFUs; 2) replacing TSV pairs obtained in step 1 with SC-TFUs followed by TSV tripling to maximize TSV fault-tolerance under wire and time constraints; and 3) performing a global clock skew tuning process on the SC-TFU embedded 3-D clock tree produced in step 2. Through out experiments, two outstanding benefits are confirmed: 1) our synthesis using SC-TFUs enables a large number of clock TSVs to be paired or tripled to ensure a very high degree of TSV fault-tolerance and 2) our synthesis flow effectively performs tuning of global clock skew whose variation is caused by the inclusion of TSV fault-tolerant cells into 3-D clock trees. | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.34, no.2, pp.266 - 279 | - |
dc.identifier.doi | 10.1109/TCAD.2014.2379645 | - |
dc.identifier.issn | 0278-0070 | - |
dc.identifier.scopusid | 2-s2.0-84921513786 | - |
dc.identifier.uri | https://scholarworks.unist.ac.kr/handle/201301/81622 | - |
dc.identifier.wosid | 000348229600009 | - |
dc.language | 영어 | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | Synthesis of TSV Fault-Tolerant 3-D Clock Trees | - |
dc.type | Article | - |
dc.description.isOpenAccess | FALSE | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Hardware & Architecture; Computer Science, Interdisciplinary Applications; Engineering, Electrical & Electronic | - |
dc.relation.journalResearchArea | Computer Science; Engineering | - |
dc.type.docType | Article | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.subject.keywordAuthor | 3-D integrated chips (ICs) | - |
dc.subject.keywordAuthor | clock skew | - |
dc.subject.keywordAuthor | clock slew | - |
dc.subject.keywordAuthor | fault-tolerant | - |
dc.subject.keywordAuthor | synthesis | - |
dc.subject.keywordAuthor | through-silicon-via (TSV) | - |
dc.subject.keywordPlus | DESIGN | - |
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