Hybrid asynchronous circuit generation amenable to conventional EDA flow

Abstract

This work proposes a new method of synthesizing asynchronous circuits targeting its practical usability. The key contribution of this work is finding an effective technique of inter-mixing the two design principles namely handshaking based single-rail and timing annotated (i.e., quasi-delay insensitive (QDI)) dual-rail of asynchronous circuits. Precisely, we propose a clever way of partitioning an input (synchronous) circuit to transform it into a circuit with single-rail and dual-rail sub-circuits and of designing seamless interface to stitch the sub circuits. Our proposed synthesis flow closely links to industrial design automation tools with standard cell libraries to enhance the practicality and productivity. Experimental results show that the designs produced by our approach expose partial or full combinations of high-performance, low-power consumption, great immunity to delay and noise variability, and mitigation to the side-channel attacks in hardware security.