A 4.86 μW/Channel Fully Differential Multi-Channel Neural Recording System

Abstract

This paper presents a fully differential multi-channel neural recording system. The system consists of four key blocks which are a low-noise amplifier (LNA), programmable gain amplifier (PGA), buffer, and successive approximation register ADC (SAR ADC). The input stage of the OTA used in LNA is designed as the inverter-based structure for improving the current efficiency. For an energy efficient system, the dual sample-and-hold (S/H) structure is applied to the SAR ADC. Each channel consumes the power of 4.86 W/Channel and achieves an input-referred noise of 2.58 Vrms. The implemented IC operates under a 1-V supply voltage for core blocks and 1.8-V for output digital buffers. The system is implemented in a standard 1P6M 0.18-m CMOS process.