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Kim, Kyung Rok
Nano-Electronic Emerging Devices (NEEDs) Lab
Research Interests
  • Nano-CMOS, neuromorphic device, terahertz (THz) plasma-wave transistor (PWT)

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A new 50-nm nMOSFET with side-gates for virtual source-drain extensions

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Title
A new 50-nm nMOSFET with side-gates for virtual source-drain extensions
Author
Choi, YJChoi, BYKim, Kyung RokLee, JDPark, BG
Keywords
50-nm nMOSFET; NAND gate; Side-gate; Virtual source/drain extension (SDE)
Issue Date
2002-10
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Citation
IEEE TRANSACTIONS ON ELECTRON DEVICES, v.49, no.10, pp.1833 - 1835
Abstract
We have proposed and fabricated a novel 50-nm nMOSFET with side-gates, which induce inversion layers for virtual source/drain extensions (SDE). The 50-nm nMOSFETs show excellent suppression of the short channel effect and reasonable current drivability [subthreshold swing of 86 mV/decade, drain-induced barrier lowering (DIBL) of 112 mV, and maximum transconductance (g(m)) of 470 muS/mum at V-D = 1.5 V], resulting from the ultra-shallow virtual SDE junction. Since both the main gate and the side-gate give good cut-off characteristics, a possible advantage of this structure in the application to multi-input NAND gates was investigated.
URI
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DOI
10.1109/TED.2002.803648
ISSN
0018-9383
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EE_Journal Papers
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