dc.citation.endPage |
33 |
- |
dc.citation.number |
1 |
- |
dc.citation.startPage |
26 |
- |
dc.citation.title |
IEEE DESIGN & TEST OF COMPUTERS |
- |
dc.citation.volume |
20 |
- |
dc.contributor.author |
Lee, Jongeun |
- |
dc.contributor.author |
Choi, K |
- |
dc.contributor.author |
Dutt, ND |
- |
dc.date.accessioned |
2023-12-22T11:36:08Z |
- |
dc.date.available |
2023-12-22T11:36:08Z |
- |
dc.date.created |
2014-10-28 |
- |
dc.date.issued |
2003-01 |
- |
dc.description.abstract |
Coarse-grained reconfigurable architectures can enhance the performance of critical loops and computation-intensive functions. Such architectures need efficient compilation techniques to map algorithms onto customized architectural configurations. A new compilation approach uses a generic reconfigurable architecture to tackle the memory bottleneck that typically limits the performance of many applications. |
- |
dc.identifier.bibliographicCitation |
IEEE DESIGN & TEST OF COMPUTERS, v.20, no.1, pp.26 - 33 |
- |
dc.identifier.doi |
10.1109/MDT.2003.1173050 |
- |
dc.identifier.issn |
0740-7475 |
- |
dc.identifier.scopusid |
2-s2.0-0037253010 |
- |
dc.identifier.uri |
https://scholarworks.unist.ac.kr/handle/201301/7927 |
- |
dc.identifier.url |
http://www.scopus.com/inward/record.url?partnerID=HzOxMe3b&scp=0037253010 |
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dc.identifier.wosid |
000180333500005 |
- |
dc.language |
영어 |
- |
dc.publisher |
IEEE COMPUTER SOC |
- |
dc.title |
Compilation approach for coarse-grained reconfigurable architectures |
- |
dc.type |
Article |
- |
dc.description.journalRegisteredClass |
scie |
- |
dc.description.journalRegisteredClass |
scopus |
- |