Fabrication of single-electron tunneling transistors with an electrically formed Coulomb island in a silicon-on-insulator nanowire
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- Fabrication of single-electron tunneling transistors with an electrically formed Coulomb island in a silicon-on-insulator nanowire
- Kim, DH; Sung, SK; Kim, Kyung Rok; Lee, JD; Park, BG
- QUANTUM-DOT; ROOM-TEMPERATURE; VOLTAGE GAIN; BLOCKADE; SWITCH; WIRE
- Issue Date
- A V S AMER INST PHYSICS
- JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, v.20, no.4, pp.1410 - 1418
- For the purpose of controllable characteristics, silicon single-electron tunneling transistors with an electrically formed Coulomb island are proposed and fabricated on the basis of the sidewall process technique. The fabricated devices are based on a silicon-on-insulator (SOI) metal-oxide-semiconductor (MOS) field effect transistor with them depletion gate. The key fabrication technique consists of two sidewall process techniques. One is the patterning of a uniform SOI nanowire, and the other is the formation of n-doped polysilicon sidewall depletion gates. While the width of a Coulomb island is determined by the width of a SOI nanowire, its length is defined by the separation between two sidewall depletion gates which are formed by a conventional lithographic process combined with the second-sidewall process. These sidewall techniques combine the conventional lithography and process technology, and guaran tee the compatibility with complementary MOS process technology. Moreover, critical dimension depends not on the lithographical limit but on the controllability of chemical vapor deposition and reactive-ion etching. Very uniform weakly p-doped SOI nanowire defined by the sidewall technique effectively suppresses unintentional tunnel junctions formed by the fluctuation of the geometry or dopant in SOI nanowire, and the Coulomb island size dependence of the device characteristics confirms the good controllability. A voltage gain larger than one and the controllability of Coulomb oscillation peak position are also successfully demonstrated, which are essential conditions for the integration of a single-electron tunneling transistor circuit. Further miniaturization and optimization of the proposed device will make room temperature designable single-electron tunneling transistors possible in the foreseeable future.
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