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Lee, Jongeun
Intelligent Computing and Codesign Lab.
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dc.citation.conferencePlace US -
dc.citation.endPage 1413 -
dc.citation.startPage 1408 -
dc.citation.title Design Automation and Test in Europe Conference -
dc.contributor.author Lee, Jungi -
dc.contributor.author Lee, Jongeun -
dc.date.accessioned 2024-01-31T22:08:09Z -
dc.date.available 2024-01-31T22:08:09Z -
dc.date.created 2021-09-10 -
dc.date.issued 2021-02 -
dc.description.abstract Coarse-grained reconfigurable architectures (CGRAs) can provide both high energy efficiency and flexibility, making them well-suited for machine learning applications. However previous work on CGRAs has a very limited support for deep neural networks (DNNs), especially for recent lightweight models such as depthwise separable convolution (DSC), which are an important workload for mobile environment. In this paper, we propose a set of architecture extensions and a mapping scheme to greatly enhance CGRA's performance for DSC kernels. Our experimental results using MobileNets demonstrate that our proposed CGRA enhancement can deliver 8 18x improvement in area-delay product depending on layer type, over a baseline CGRA with a state-of-the-art CGRA compiler. Moreover, our proposed CGRA architecture can also speed up 3D convolution with similar efficiency as previous work, demonstrating the effectiveness of our architectural features beyond DSC layers. -
dc.identifier.bibliographicCitation Design Automation and Test in Europe Conference, pp.1408 - 1413 -
dc.identifier.doi 10.23919/DATE51398.2021.9474256 -
dc.identifier.issn 1530-1591 -
dc.identifier.scopusid 2-s2.0-85111068413 -
dc.identifier.uri https://scholarworks.unist.ac.kr/handle/201301/77642 -
dc.language 영어 -
dc.publisher Institute of Electrical and Electronics Engineers Inc. -
dc.title NP-CGRA: Extending CGRAs for Efficient Processing of Light-weight Deep Neural Networks -
dc.type Conference Paper -
dc.date.conferenceDate 2021-02-01 -

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