6-inch Semiconductor FAB Alliance for Developing Low-Power FEOL Integration Processes

Abstract

As a part of the recent government-supported program for establishing the semiconductor process integration platform to develop new types of low-power CMOS device, the 6-inch full process flow has been developed by combining ETRI, UNIST, and DGIST FABs. The FETs based on the ferroelectric gate insulator such as ferroelectric FET (FeFET) and negative-capacitance FET (NC-FET) have been pursued as the first target of low-power device. The overall structure of 6-inch FAB alliance including the roll allocation of each FAB in developing individual unit processes will be introduced together with the outcomes of development activities. Especially, the ferroelectric gate stack fabricated by using thin film deposition and dry etching processes will be discussed regarding its structural completeness and electrical properties. Additionally, the operational performances of the test elements on the wafers that have gone through the entire processes (first full run) will be presented in conjunction with some issues encountered in combining the three FABs to construct a seamless 6-inch full process flow.