Analytical Probability Density Calculation of Power-Supply-Induced Jitter in high-speed Tx circuits

Abstract

As the speed of I/O interface has increased up to multi-gigabit data rates [1], the research of signal integrity issues for the I/O channel is more demanding. The statistical approach to get jitter in time domain can reduce computational time and effort compared to the typical transient SPICE simulations. In this paper, the output voltage waveforms of the multi-stage buffers are calculated with simpler analytical solutions. The driving non-linear MOSFETs are replaced by Thevenin equivalent voltages and impedances, and the solutions of differential equations can be simply expressed with corresponding impulse responses. Also, the jitter induced by the supply voltage fluctuations can be calculated. The supply voltage fluctuations in the time domain are directly convolved with the impulse responses to obtain the output waveforms. The validation of the proposed analytic method is done by experiments. In the experiments, the voltage fluctuations in time domain are measured both at the integrated circuit (IC) and printed circuit board (PCB) pads simultaneously. Then, the on-chip supply voltage fluctuations are extracted from the measured results. The Power Distribution Network (PDN) of the IC and PCB are modeled from impedance measurements on the pads. Using the PDN model, the measured power and ground voltage fluctuations are validated with the SPICE simulation. The output off-chip channel of the victim buffer can be modeled as parasitic inductances and capacitances from the measured two-port S-parameters at the designed PCB channel. As the number of buffer stages connected to the fluctuating supply voltages are varied from one to three in the experiments, the effect on the output waveform induced by supply voltage fluctuations can be investigated. The calculated step responses and jitter PDFs of the multi-stage buffers are all validated with measured output waveforms and jitter histograms. In addition, the Electrostatic discharge (ESD) protection structures which are commonly employed at near the I/O pins can induce parasitic junction capacitance (CESD) and parasitic resistance (RESD) causing parasitic effects. Thus, the supply voltage fluctuations also can couple through ESD parasitic. The step responses of a linear output driver with silicon interposer channel are derived including the parasitics of ESD protection circuits. The probability density functions of the output voltage due to supply voltage fluctuations are also analytically calculated. With changing the frequency of supply voltage fluctuations, the effect of ESD parasitics on the output jitter is calculated and compared.