Enhanced Trapped-Charge Memory Effect in Graphene Field Effect Transistor with Al2O3/SiO2 Gate Insulator Stack

Abstract

Graphene is a single layer of carbon atoms arranged in a honeycomb lattice, and it has attracted significant attention thanks to its intriguing electronic, thermal, and mechanical properties. This work explores the influence of an Al2O3 overlayer deposited on the SiO2 gate insulator of a conventional back-gated graphene field effect transistor (GFET) on its operational characteristics. A graphene film is synthesized via chemical vapor deposition on a copper foil (Graphenea) and transferred onto the SiO₂ and Al₂O₃/SiO₂ gate insulators by using the semi-dry transfer method [1]. The Al₂O₃ layer is relatively thin with its thickness of 12nm while the SiO₂ layer is 100nm thick. Raman spectrum measurements are performed to figure out the doping type and density of graphene channel just after the transfer process. The 2D peaks for graphene on SiO₂ and Al₂O₃/SiO₂ surfaces are found at ~2681 and ~2673 cm-1, respectively, while the G peaks are found at ~1591 and ~1585 cm-1, respectively. These peak positions, blue-shifted compared with those of intrinsic graphene confirm p-type doping on both surfaces with a higher hole concentration on SiO₂ surface being expected. The graphene channel is patterned through photolithography processes preceded by the formation of Au/Ti electrodes (50nm/20nm) near the opposite edges of channel serving as source and drain contacts. The noticeable hysteretic behaviors in the transfer curves revealing drain-to-source current (IDS) vs. gate voltage (Vg) are observed for both SiO2 and Al2O3/SiO2 gate insulators, considered to originate from the electron trapping and detrapping in the insulators. This hysteretic behavior indicates that the carrier type and density in the graphene channel are modulated by the degree of electron trapping in the gate insulator (memory state). The memory retention measurements are followed by applying triangular pulses of +60 and -60 V to the back gate of GFET and measuring the IDS at Vg = 0 V over an observation period of ~ 60,000 seconds. The GFETs with Al₂O₃/SiO2 gate insulator stack exhibit significantly stronger memory effects compared to SiO₂ gate insulator. Our work suggests that the GFET adopting the back-gate configuration with Al2O3/SiO2 gate insulator stack can be a promising alternative charge-trapping memory structure to the conventional Oxide-Nitride-Oxide structure.

[1] Sungchul Jung, et al., Journal of Applied Physics 125, 184302 (2019)