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DC Field | Value | Language |
---|---|---|
dc.citation.endPage | 5231 | - |
dc.citation.number | 12 | - |
dc.citation.startPage | 5220 | - |
dc.citation.title | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | - |
dc.citation.volume | 41 | - |
dc.contributor.author | Choi, Jooyeon | - |
dc.contributor.author | Sim, Hyeonuk | - |
dc.contributor.author | Oh, Sangyun | - |
dc.contributor.author | Lee, Sugil | - |
dc.contributor.author | Lee, Jongeun | - |
dc.date.accessioned | 2023-12-21T13:14:28Z | - |
dc.date.available | 2023-12-21T13:14:28Z | - |
dc.date.created | 2022-11-28 | - |
dc.date.issued | 2022-12 | - |
dc.description.abstract | In this paper we propose a novel logarithmic quantization-based DNN (Deep Neural Network) architecture for depthwise separable convolution (DSC) networks. Our architecture is based on selective two-word logarithmic quantization (STLQ), which improves accuracy greatly over logarithmic-scale quantization while retaining the speed and area advantage of logarithmic quantization. On the other hand, it also comes with the synchronization problem due to variable-latency PEs (processing elements), which we address through a novel architecture and a compile-time optimization technique. Our architecture is dynamically reconfigurable to support various combinations of depthwise vs. pointwise convolution layers efficiently. Our experimental results using layers from MobileNetV2 and ShuffleNetV2 demonstrate that our architecture is significantly faster and more area-efficient than previous DSC accelerator architectures as well as previous accelerators utilizing logarithmic quantization. | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.41, no.12, pp.5220 - 5231 | - |
dc.identifier.doi | 10.1109/tcad.2022.3150249 | - |
dc.identifier.issn | 0278-0070 | - |
dc.identifier.scopusid | 2-s2.0-85124741466 | - |
dc.identifier.uri | https://scholarworks.unist.ac.kr/handle/201301/60049 | - |
dc.identifier.wosid | 000906580100007 | - |
dc.language | 영어 | - |
dc.publisher | Institute of Electrical and Electronics Engineers | - |
dc.title | MLogNet: A Logarithmic Quantization-Based Accelerator for Depthwise Separable Convolution | - |
dc.type | Article | - |
dc.description.isOpenAccess | FALSE | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Hardware & Architecture;Computer Science, Interdisciplinary Applications;Engineering, Electrical & Electronic | - |
dc.relation.journalResearchArea | Computer Science;Engineering | - |
dc.type.docType | Article | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.subject.keywordAuthor | logarithmic quantization | - |
dc.subject.keywordAuthor | Neural networks | - |
dc.subject.keywordAuthor | Quantization (signal) | - |
dc.subject.keywordAuthor | Synchronization | - |
dc.subject.keywordAuthor | variable-latency multiplication | - |
dc.subject.keywordAuthor | channel reordering. | - |
dc.subject.keywordAuthor | Computer architecture | - |
dc.subject.keywordAuthor | Convolution | - |
dc.subject.keywordAuthor | Deep learning | - |
dc.subject.keywordAuthor | Deep learning processor | - |
dc.subject.keywordAuthor | depthwise separable convolution | - |
dc.subject.keywordAuthor | Hardware acceleration | - |
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