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Jeong, Changwook
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dc.citation.conferencePlace US -
dc.citation.conferencePlace Honolulu, HI -
dc.citation.endPage 21 -
dc.citation.startPage 20 -
dc.citation.title 2004 Symposium on VLSI Technology -
dc.contributor.author Lee, S.H. -
dc.contributor.author Hwang, Y.N. -
dc.contributor.author Lee, S.Y. -
dc.contributor.author Ryoo, K.C. -
dc.contributor.author Ahn, S.J. -
dc.contributor.author Koo, H.C. -
dc.contributor.author Jeong, Changwook -
dc.contributor.author Kim, Y.-T. -
dc.contributor.author Koh, G.H. -
dc.contributor.author Jeong, G.T. -
dc.contributor.author Jeong, H.S. -
dc.contributor.author Kim, K. -
dc.date.accessioned 2023-12-20T06:05:59Z -
dc.date.available 2023-12-20T06:05:59Z -
dc.date.created 2022-04-06 -
dc.date.issued 2004-61-05 -
dc.description.abstract We have integrated a 64Mb nonvolatile random access memory using phase transition phenomena. Based on 0.18um-CMOS technologies, the vertical contact typed memory cell is fabricated. The device density can be sharply increased with decreasing the writing current and the GST size. But, for reduction of writing current, issues including set and interface resistances should be stabilized. Additionally, our results also show the feasibility of 256Mb nonvolatile PRAM with writing time below 100ns. -
dc.identifier.bibliographicCitation 2004 Symposium on VLSI Technology, pp.20 - 21 -
dc.identifier.doi 10.1109/vlsit.2004.1345369 -
dc.identifier.issn 0743-1562 -
dc.identifier.scopusid 2-s2.0-4544367628 -
dc.identifier.uri https://scholarworks.unist.ac.kr/handle/201301/58545 -
dc.language 영어 -
dc.publisher Institute of Electrical and Electronics Engineers Inc. -
dc.title Full integration and cell characteristics for 64Mb nonvolatile PRAM -
dc.type Conference Paper -
dc.date.conferenceDate 2004-06-15 -

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