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Lee, Jongeun
Intelligent Computing and Codesign Lab.
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dc.citation.endPage 3399 -
dc.citation.number 10 -
dc.citation.startPage 3387 -
dc.citation.title IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS -
dc.citation.volume 41 -
dc.contributor.author Lee, Jungi -
dc.contributor.author Lee, Jongeun -
dc.date.accessioned 2023-12-21T13:39:15Z -
dc.date.available 2023-12-21T13:39:15Z -
dc.date.created 2022-01-06 -
dc.date.issued 2022-10 -
dc.description.abstract DNN (Deep Neural Network) processing units, or DPUs, are one of the most energy-efficient platforms for DNN applications. However, designing new DPUs for every DNN model is very costly and time-consuming. In this paper we propose an alternative approach: to specialize coarse-grained reconfigurable architectures (CGRAs), which are already quite capable of delivering high performance and high energy efficiency for compute-intensive kernels. We identify a small set of architectural features on a baseline CGRA to enable high performance mapping of depthwise convolution (DWC) and pointwise convolution (PWC) kernels, which are the most important building block in recent light-weight DNN models. Our experimental results using MobileNets demonstrate that our proposed CGRA enhancement can deliver 8 18× improvement in area-delay product depending on layer type, over a baseline CGRA with a state-of-the-art CGRA compiler. Moreover, our proposed CGRA architecture can also speed up 3D convolution with similar efficiency as previous work, demonstrating the effectiveness of our architectural features beyond depthwise separable convolution layers. -
dc.identifier.bibliographicCitation IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.41, no.10, pp.3387 - 3399 -
dc.identifier.doi 10.1109/tcad.2021.3123178 -
dc.identifier.issn 0278-0070 -
dc.identifier.scopusid 2-s2.0-85118597566 -
dc.identifier.uri https://scholarworks.unist.ac.kr/handle/201301/55916 -
dc.identifier.wosid 000856129900021 -
dc.language 영어 -
dc.publisher Institute of Electrical and Electronics Engineers -
dc.title Specializing CGRAs for Light-Weight Convolutional Neural Networks -
dc.type Article -
dc.description.isOpenAccess FALSE -
dc.relation.journalWebOfScienceCategory Computer Science, Hardware & Architecture;Computer Science, Interdisciplinary Applications;Engineering, Electrical & Electronic -
dc.relation.journalResearchArea Computer Science;Engineering -
dc.type.docType Article -
dc.description.journalRegisteredClass scie -
dc.description.journalRegisteredClass scopus -
dc.subject.keywordAuthor Coarse-grained reconfigurable architecture (CGRA) -
dc.subject.keywordAuthor convolutional neural network (CNN) -
dc.subject.keywordAuthor depthwise separable convolution (DSC) -
dc.subject.keywordAuthor neural processing unit -
dc.subject.keywordPlus ARCHITECTURES -
dc.subject.keywordPlus ACCELERATOR -

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