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윤태식

Yoon, Tae-Sik
Nano Semiconductor Research Lab.
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Surface roughness and dislocation distribution in compositionally graded relaxed SiGe buffer layer with inserted-strained Si layers

Author(s)
Yoon, Tae-SikLiu, JNoori, AMGoorsky, MSXie, YH
Issued Date
2005-07
DOI
10.1063/1.1988986
URI
https://scholarworks.unist.ac.kr/handle/201301/50303
Citation
APPLIED PHYSICS LETTERS, v.87, no.1
Abstract
We investigate the surface roughness and dislocation distribution of compositionally graded relaxed SiGe buffer layers by inserting two tensile-strained Si layers. The 20 nm thick strained Si layers, less than the critical thickness for dislocation formation, are inserted at 10 and 20% Ge content regions of the 1 mu m thick graded SiGe layer with a final Ge content of 30%. The surface immediately after growing the second strained Si layer on SiGe with 20% Ge content is found to be flat with about 1.1 nm root-mean-square roughness. However, the crosshatched surface with the 7.8 nm roughness develops during subsequent SiGe growths, which is slightly less than the 10.3 nm value for SiGe without inserted Si layers. Another important issue of consideration is that inserting the strained Si layers leads to increased interaction among dislocations as shown by cross-sectional transmission electron microscopy. This study explores the possibility of using strained layers for achieving flat surfaces and illustrates the need for optimization when using this approach. (c) 2005 American Institute of Physics.
Publisher
AMER INST PHYSICS
ISSN
0003-6951
Keyword
FIELD-EFFECT TRANSISTORSSI1-XGEX/SI HETEROSTRUCTURESRELAXATIONMISFITFILMSSUPERLATTICESFABRICATIONMORPHOLOGY

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