0.18-mu m CMOS equalization techniques for 10-Gb/s fiber optical communication links
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- 0.18-mu m CMOS equalization techniques for 10-Gb/s fiber optical communication links
- Maeng, M; Bien, Franklin; Hur, Y; Kim, H; Chandramouli, S; Gebara, E; Laskar, J
- 0.18-μm CMOS; 10-gb/s; Active inductive peaking; Delay-locked loop (DLL); Equalization; Feed-forward equalizer (FFE); Finite impulse response (FIR) filter; Input/output (I/O) interconnection; LC ladder; Multimode fiber (MMF); Nonreturn to zero (NRZ)
- Issue Date
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, v.53, no.11, pp.3509 - 3519
- Limitations in data transmission caused by modal dispersion in fiber-optic links can be significantly improved using equalization techniques. In this paper, two different equalizer implementation approaches are proposed to extend the transmission capacities of existing fiber-optic links. The building blocks of the equalizer including a multiplier cell, a delay line, and an output buffer stage are fully integrated on a 0.18-μm CMOS process. For the continuous-time tap-delay implementation, a passive LC delay line and an active inductance peaking delay line are compared for performance against process variation, as well as power consumption. In addition, a delay-locked loop is proposed to counter delay variations caused by changes in the process corner. A 10-Gb/s nonreturn-to-zero signal is received after transmission through a 500-m multimode-fiber channel, and the signal impairment due to the differential modal delay is successfully compensated using both feed-forward equalizers.
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