Edge-over Schottky Barrier MOSFET for Achieving Ideal Subthreshold Slope in Nanometer Scale

Abstract

As the device size shrinks continuously by scaling in the current Si CMOS technology, the drain induced barrier lowering (DIBL) that is one of short channel effects and causes the increase of sub-threshold slope and leakage current become severe more and more in device operation. We propose a new device structure, edge-over Schottky barrier field effect transistor (SBFET), suppressing DIBL efficiently. Edge-over SBFET has a unique pier structure where the transistor channel is elongated by going over the edge of pier. Hence, an edge-over SBFET has a much longer channel compared with a planar FET with the same transistor pitch. The interfaces between a thin poly-silicon channel and Al electrodes (source and drain) form Schottky jucntions with small Schottky barriers < 0.2 eV. We performed 2-dimensional TCAD modeling on an edge-over SBFET with horizontal channel length of 5.5 nm and ultra-thin channel thickness of 2 nm. The TCAD modeling predicts subthreshold slope of ~71 mV/dec and OFF-state current of ~8 nA. It is also noticed that DIBL gets suppressed further as the pier height increases.