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Lee, Jongeun
Renew: Reconfigurable and Neuromorphic Computing Lab
Research Interests
  • Reconfigurable processor architecture, neuromorphic processor, stochastic computing

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Improving Performance of Nested Loops on Reconfigurable Array Processors

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dc.contributor.author Kim, Yongjoo ko
dc.contributor.author Lee, Jongeun ko
dc.contributor.author Mai, Toan X. ko
dc.contributor.author Paek, Yunheung ko
dc.date.available 2014-04-10T02:22:24Z -
dc.date.created 2013-06-20 ko
dc.date.issued 2012-01 -
dc.identifier.citation ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, v.8, no.4, pp.1 - 23 ko
dc.identifier.issn 1544-3566 ko
dc.identifier.uri https://scholarworks.unist.ac.kr/handle/201301/3814 -
dc.identifier.uri http://www.scopus.com/inward/record.url?partnerID=HzOxMe3b&scp=84863291580 ko
dc.description.abstract Pipelining algorithms are typically concerned with improving only the steady-state performance, or the kernel time. The pipeline setup time happens only once and therefore can be negligible compared to the kernel time. However, for Coarse-Grained Reconfigurable Architectures (CGRAs) used as a coprocessor to a main processor, pipeline setup can take much longer due to the communication delay between the two processors, and can become significant if it is repeated in an outer loop of a loop nest. In this paper we evaluate the overhead of such non-kernel execution times when mapping nested loops for CGRAs, and propose a novel architecture-compiler cooperative scheme to reduce the overhead, while also minimizing the number of extra configurations required. Our experimental results using loops from multimedia and scientific domains demonstrate that our proposed techniques can greatly increase the performance of nested loops by up to 2.87 times compared to the conventional approach of accelerating only the innermost loops. Moreover, the mappings generated by our techniques require only a modest number of configurations that can fit in recent reconfigurable architectures. ko
dc.description.statementofresponsibility close -
dc.language ENG ko
dc.publisher ASSOC COMPUTING MACHINERY ko
dc.subject Co-processors ko
dc.subject Coarse grained reconfigurable architecture ko
dc.subject Communication delays ko
dc.subject Compilation ko
dc.subject Conventional approach ko
dc.subject Cooperative schemes ko
dc.subject Execution time ko
dc.subject Improving performance ko
dc.subject Loop nests ko
dc.subject Nested Loops ko
dc.subject Outer loop ko
dc.subject Reconfigurable array ko
dc.subject Set-up time ko
dc.subject Software pipelining ko
dc.subject Steady state performance ko
dc.subject Two processors ko
dc.title Improving Performance of Nested Loops on Reconfigurable Array Processors ko
dc.type ARTICLE ko
dc.identifier.scopusid 2-s2.0-84863291580 ko
dc.identifier.wosid 000299995000015 ko
dc.type.rims ART ko
dc.description.wostc 0 *
dc.description.scopustc 7 *
dc.date.tcdate 2015-02-28 *
dc.date.scptcdate 2014-08-20 *
dc.identifier.doi 10.1145/2086696.2086711 ko
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