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Lee, Jongeun
Renew: Reconfigurable and Neuromorphic Computing Lab
Research Interests
  • Reconfigurable processor architecture, neuromorphic processor, stochastic computing

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Static Analysis of Register File Vulnerability

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dc.contributor.author Lee, Jongeun ko
dc.contributor.author Shrivastava, Aviral ko
dc.date.available 2014-04-10T01:43:53Z -
dc.date.created 2013-06-18 ko
dc.date.issued 2011-04 -
dc.identifier.citation IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.30, no.4, pp.607 - 616 ko
dc.identifier.issn 0278-0070 ko
dc.identifier.uri https://scholarworks.unist.ac.kr/handle/201301/3340 -
dc.identifier.uri http://www.scopus.com/inward/record.url?partnerID=HzOxMe3b&scp=79953082183 ko
dc.description.abstract With continuous technology scaling, soft errors are becoming an increasingly important design concern even for earth-bound applications. While compiler approaches have the potential to mitigate the effect of soft errors with minimal runtime overheads, static vulnerability estimation-an essential part of compiler approaches-is lacking due to its inherent complexity. This paper presents a static analysis approach for register file (RF) vulnerability estimation. We decompose the vulnerability of a register into intrinsic and conditional basic-block vulnerabilities. This decomposition allows us to develop a fast, yet reasonably accurate RF vulnerability estimation mechanism. We validate and compare a linear equation based method and an iterative method. Also we demonstrate a practical application of RF vulnerability estimation to compiler optimizations. Our experimental results on benchmarks from MiBench suite indicate that not only our static RF vulnerability estimation is fast and accurate, but also compiler optimizations enabled by our static estimation can achieve very cost-effective protection of register files against soft errors. ko
dc.description.statementofresponsibility close -
dc.language ENG ko
dc.publisher IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC ko
dc.subject Analysis approach ko
dc.subject Architectural vulnerability factor ko
dc.subject Compiler optimizations ko
dc.subject compilers ko
dc.subject Cost-effective protection ko
dc.subject Inherent complexity ko
dc.subject partially protected register file ko
dc.subject Register files ko
dc.subject Runtime overheads ko
dc.subject soft error ko
dc.subject Static estimation ko
dc.subject Technology scaling ko
dc.title Static Analysis of Register File Vulnerability ko
dc.type ARTICLE ko
dc.identifier.scopusid 2-s2.0-79953082183 ko
dc.identifier.wosid 000288678400012 ko
dc.type.rims ART ko
dc.description.scopustc 6 *
dc.date.scptcdate 2014-07-12 *
dc.identifier.doi 10.1109/TCAD.2010.2095630 ko
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