dc.citation.conferencePlace |
FR |
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dc.citation.conferencePlace |
Grenoble; France |
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dc.citation.endPage |
1578 |
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dc.citation.startPage |
1575 |
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dc.citation.title |
Design Automation and Test in Europe Conference |
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dc.contributor.author |
Lee, Jongeun |
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dc.contributor.author |
Jeong, Yeonghun |
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dc.contributor.author |
Seo, Sungsok |
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dc.date.accessioned |
2023-12-20T01:08:33Z |
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dc.date.available |
2023-12-20T01:08:33Z |
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dc.date.created |
2013-07-17 |
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dc.date.issued |
2013-03-18 |
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dc.description.abstract |
While Coarse-Grained Reconfigurable Architectures (CGRAs) are very efficient at handling regular, compute-intensive loops, their weakness at control-intensive processing and the need for frequent reconfiguration require another processor, for which usually a main processor is used. To minimize the overhead arising in such collaborative execution, we integrate a dedicated sequential processor (SP) with a reconfigurable array (RA), where the crucial problem is how to share the memory between SP and RA while keeping the SP's memory access latency very short. We present a detailed architecture, control, and program example of our approach, focusing on our optimized on-chip shared memory organization between SP and RA. Our preliminary results demonstrate that our optimized memory architecture is very effective in reducing keruel execution times (23.5% compared to a more straightforward alteruative), and our approach can reduce the RA control overhead and other sequential code execution time in kernels significantly, resulting in up to 23.1 % reduction in kernel execution time, compared to the conventional system using the main processor for sequential code execution. |
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dc.identifier.bibliographicCitation |
Design Automation and Test in Europe Conference, pp.1575 - 1578 |
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dc.identifier.doi |
10.7873/DATE.2013.320 |
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dc.identifier.issn |
1530-1591 |
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dc.identifier.scopusid |
2-s2.0-84885597472 |
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dc.identifier.uri |
https://scholarworks.unist.ac.kr/handle/201301/32838 |
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dc.identifier.url |
https://ieeexplore.ieee.org/document/6513766/ |
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dc.language |
영어 |
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dc.publisher |
IEEE/ACM |
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dc.title |
Fast shared on-chip memory architecture for efficient hybrid computing with CGRAs |
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dc.type |
Conference Paper |
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dc.date.conferenceDate |
2013-03-18 |
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