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Baek, Woongki
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IACM: Integrated adaptive cache management for high-performance and energy-efficient GPGPU computing

Author(s)
Kim, Kyu YeunPark, JinsuBaek, Woongki
Issued Date
2016-10-02
DOI
10.1109/ICCD.2016.7753308
URI
https://scholarworks.unist.ac.kr/handle/201301/32783
Fulltext
http://ieeexplore.ieee.org/document/7753308/
Citation
IEEE International Conference on Computer Design, pp.380 - 383
Abstract
Hardware caches are widely employed in GPGPUs to achieve higher performance and energy efficiency. Incorporating hardware caches in GPGPUs, however, does not immediately guarantee enhanced performance and energy efficiency due to high cache contention and thrashing. To address the inefficiency of GPGPU caches, various adaptive techniques (e.g., warp limiting) have been proposed. However, relatively little work has been done in the context of creating an architectural framework that tightly integrates adaptive cache management techniques and investigating their effectiveness and interaction. To bridge this gap, we propose IACM, integrated adaptive cache management for high-performance and energy-efficient GPGPU computing. IACM integrates the state-of-the-art adaptive cache management techniques (i.e., cache indexing, bypassing, and warp limiting) in a unified architectural framework. Our quantitative evaluation demonstrates that IACM significantly improves the performance and energy efficiency of various GPGPU workloads over the baseline architecture (i.e., 98.1% and 61.9% on average).
Publisher
34th IEEE International Conference on Computer Design, ICCD 2016

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