dc.citation.conferencePlace |
SZ |
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dc.citation.conferencePlace |
SwissTech Convention CenterSwisstech, Lausanne |
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dc.citation.endPage |
893 |
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dc.citation.startPage |
890 |
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dc.citation.title |
Design Automation and Test in Europe Conference |
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dc.contributor.author |
Nguyen, Dong |
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dc.contributor.author |
Kim, Daewoo |
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dc.contributor.author |
Lee, Jongeun |
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dc.date.accessioned |
2023-12-19T19:11:33Z |
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dc.date.available |
2023-12-19T19:11:33Z |
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dc.date.created |
2017-08-14 |
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dc.date.issued |
2017-03-27 |
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dc.description.abstract |
This paper presents a novel method to double the computation rate of convolutional neural network (CNN) accelerators by packing two multiply-and-accumulate (MAC) operations into one DSP block of off-the-shelf FPGAs (called Double MAC). While a general SIMD MAC using a single DSP block seems impossible, our solution is tailored for the kind of MAC operations required for a convolution layer. Our preliminary evaluation shows that not only can our Double MAC approach increase the computation throughput of a CNN layer by twice with essentially the same resource utilization, the network level performance can also be improved by 14∼84% over a highly optimized state-of-the-art accelerator solution depending on the CNN hyper-parameters. |
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dc.identifier.bibliographicCitation |
Design Automation and Test in Europe Conference, pp.890 - 893 |
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dc.identifier.doi |
10.23919/DATE.2017.7927113 |
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dc.identifier.scopusid |
2-s2.0-85020213228 |
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dc.identifier.uri |
https://scholarworks.unist.ac.kr/handle/201301/32773 |
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dc.identifier.url |
http://ieeexplore.ieee.org/document/7927113/ |
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dc.language |
영어 |
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dc.publisher |
20th Design, Automation and Test in Europe, DATE 2017 |
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dc.title |
Double MAC: Doubling the Performance of Convolutional Neural Networks on Modern FPGAs |
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dc.type |
Conference Paper |
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dc.date.conferenceDate |
2017-03-27 |
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