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Lee, Jaiyong
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Performance of an input-queued ATM switch with even/odd switching planes

Author(s)
Son, JWLee, HTOh, YYLee, JaiyongLee, SB
Issued Date
1997-07
DOI
10.1049/el:19970837
URI
https://scholarworks.unist.ac.kr/handle/201301/32128
Fulltext
https://ieeexplore.ieee.org/document/603563/?arnumber=603563&tag=1
Citation
ELECTRONICS LETTERS, v.33, no.14, pp.1192 - 1193
Abstract
A switch architecture is proposed for alleviating the HOL blocking by employing even/odd dual FIFO queues at each input and even/odd dual switching planes dedicated to each even/odd queue. Under random traffic, it gives 76.4% throughput without output expansion and 100% with output expansion r = 2, with the same amount of crosspoints as for the ordinary output expansion scheme.
Publisher
IEE-INST ELEC ENG
ISSN
0013-5194
Keyword (Author)
asynchronous transfer modeswitching systems

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