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정홍식

Jeong, Hongsik
Future Semiconductor Technology Lab.
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Robust two-dimensional stack capacitor technologies for 64 Mbit one-transistor-one-capacitor ferroelectric random access memory

Author(s)
Jung, Ju-YoungJoo, Heung-JinPark, Jung-HoonKang, Seuno-KukKim, Hwi-SanChoi, Do-YeonKim, Jai-HyunLee, Eun-SunHong, Young-KiKim, Hyun-HoJung, Dong-JinKang, Young-MinLee, Sung-YungJeong, Hong-SikKim, Kinam
Issued Date
2007-04
DOI
10.1143/JJAP.46.1934
URI
https://scholarworks.unist.ac.kr/handle/201301/27153
Fulltext
https://iopscience.iop.org/article/10.1143/JJAP.46.1934
Citation
JAPANESE JOURNAL OF APPLIED PHYSICS, v.46, no.4B, pp.1934 - 1937
Abstract
It is very important to develop capacitor module technologies such as robust Pb(ZrxTi1-x)O-3 (PZT) film technology at nm scaled PZT thickness and damage minimized ferroelectric capacitor etching technology are crucial for the success of high density one-transistor-one-capacitor (1T1C) ferroelectric random access memory (FRAM). We resolved this issue from the change of the capacitor etching system and optimization of the PZT/SrRuO3 (SRO) deposition process. As a result, we realized a highly reliable sensing window for 64 Mbit 1T1C FRAM that were realized by novel technologies such as robust MOCVD PZT deposition technologies, optimized SRO electrode and damage minimized ferroelectric capacitor etching technologies.
Publisher
IOP PUBLISHING LTD
ISSN
0021-4922
Keyword (Author)
FRAM64Mbit1T1CferroelectricPZT

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