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Kim, Jae Joon
Convergence Semiconductor Design Lab (CSDL)
Research Interests
  • Integrated circuits and systems, smart sensor interfaces, wearable healthcare systems, IoT & automotive electronics, mixed-mode circuits

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A low-power/high-resolution dual-mode analog-to-digital converter for wireless sensor applications

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Title
A low-power/high-resolution dual-mode analog-to-digital converter for wireless sensor applications
Author
Kim, Jae JoonCho, Chang-HyukChae, Kwan-YeobByun, Sangjin
Keywords
Analog to digital converters; CMOS processs; Dual modes; Dual-mode architecture; Dual-mode operation; High resolution; Integrating resolution booster; Low Power; Low-power mode; SAR ADC; Successive approximation register; Successive approximation register analogto-digital converters (ADC); Total power consumption; Wireless sensor
Issue Date
2011-10
Publisher
IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
Citation
IEICE ELECTRONICS EXPRESS, v.8, no.20, pp.1730 - 1735
Abstract
A successive approximation register (SAR) analog-to-digital converter (ADC) with an integrating resolution booster (IRB) is proposed and experimentally verified to provide the capability of dual-mode operation, that is, low-power and high-resolution modes. This dual-mode architecture corresponds to a kind of hybrid ADC architecture, combining a low-power SAR ADC and a high-resolution integrating-type ADC together. A prototype ADC design is fabricated in a 0.18 mu m CMOS process, and its dual-mode operation is experimentally verified. The total power consumption in the low-power mode was only 8 mu W with the resolution of 6 bits, and the high-resolution mode achieved an additional resolution of 4 bits by activating the IRB, consuming the instant power of 380 mu W.
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DOI
10.1587/elex.8.1730
ISSN
1349-2543
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ECE_Journal Papers
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