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Kim, Jae Joon
Circuits & Systems Design Lab.
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Simple odd number frequency divider with 50% duty cycle

Author(s)
Byun, SangjinSon, Chung HwanKim, Jae Joon
Issued Date
2012-08
DOI
10.1587/elex.9.1249
URI
https://scholarworks.unist.ac.kr/handle/201301/2561
Fulltext
http://www.scopus.com/inward/record.url?partnerID=HzOxMe3b&scp=84865192349
Citation
IEICE ELECTRONICS EXPRESS, v.9, no.15, pp.1249 - 1253
Abstract
A simple odd number frequency divider with 50% duty cycle is presented. The odd number frequency divider consists of a general odd number counter and the proposed duty cycle trimming circuit. The duty cycle trimming circuit can output 50% duty cycle with only additional six transistors. A prototype divide-by-5 circuit with 50% duty cycle was implemented for a 500-Mb/s similar to 5.6-Gb/s 1:10 CDR/DEMUX IC in a 0.13 mu m 1P8M CMOS process.
Publisher
IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
ISSN
1349-2543
Keyword (Author)
odd number frequency dividerduty cycle

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