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Choi, Jaehyouk
Integrated Circuits and Systems Lab (ICSL)
Research Interests
  • RF/Analog/Mixed IC design, low power CMOS IC, wired/wireless TRX IC, clock generation IC

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A 0.56-2.92 GHz Wideband and Low Phase Noise Quadrature LO-Generator Using a Single LC-VCO for 2G-4G Multistandard Cellular Transceivers

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Title
A 0.56-2.92 GHz Wideband and Low Phase Noise Quadrature LO-Generator Using a Single LC-VCO for 2G-4G Multistandard Cellular Transceivers
Author
Yoon, HeeinLee, YoungsunLim, YounghyunTak, GuemyoungKim, HongdeukHo, YocheolChoi, Jaehyouk
Issue Date
2016-03
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Citation
IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.51, no.3, pp.614 - 625
Abstract
A wideband and low phase noise quadrature local oscillation (LO) signal generator for multi-standard cellular transceivers was proposed. Using the new LO-plan consisting of divide-by-6, divide-by-4, and divide-by-12 frequency dividers, the required frequency tuning range (FTR) of a VCO was reduced to 39%, which can be easily covered by a single LC-VCO. Due to the reduced FTR, the VCO can retain a high Q-factor and achieve low phase noise. The key building block of the new LO-plan is a quadrature divide-by-6 divider, capable of generating precise I/Q signals. To implement the quadrature divide-by-6 divider, we proposed a fully differential divide-by-3 divider with 50% duty cycle. Using the same idea, a fully differential divide-by-2 circuit was also proposed for divide-by-4 and divide-by-12 dividers. The proposed LO-generator was fabricated in a 40-nm CMOS process, and covered LO-frequencies of 0.56 - 2.92 GHz for multi-standard cellular transceivers. The LO-generator occupied a small silicon area of 0.15 mm2 and achieved an excellent phase noise performance of -141.02 dBc/Hz at a 1-MHz offset from a 709-MHz LO-frequency.
URI
https://scholarworks.unist.ac.kr/handle/201301/18055
URL
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7378410
DOI
10.1109/JSSC.2015.2510019
ISSN
0018-9200
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