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A 0.1-1.5-GHz Wide Harmonic-Locking-Free Delay-Locked Loop Using an Exponential DAC File

Park, Suneui , Kim, Juyeop , Hwang, Chanwoong , Park, Hangi , Yoo, Seyeon , Seong, Taeho , Choi, Jaehyouk

Article Issue Date2019-08 View26
A 170MHz-Lock-In-Range and −253dB-FoMjitter 12-to-14.5GHz Subsampling PLL with a 150µW Frequency-Disturbance-Correcting Loop Using a Low-Power Unevenly Spaced Edge Generator File

Lim, Younghyun , Kim, Juyeop , Jo, Yongwoo , Bang, Jooeun , Yoo, Seyeon , Park, Hangi , Yoon, Heein , Choi, Jaehyouk

Conference Paper Issue Date2020-02-16 View30
A Low-Jitter and Low-Fractional-Spur Ring-DCO-Based Fractional-N Digital PLL Using a DTC's Second-/Third-Order Nonlinearity Cancellation and a Probability-Density-Shaping Delta sigma M File

Hwang, Chanwoong , Park, Hangi , Lee, Yongsun , Seong, Taeho , Choi, Jaehyouk

Article Issue Date2022-09 View19
A −58dBc-Worst-Fractional-Spur and −234dB-FoMjitter, 5.5GHz Ring-DCO-Based Fractional-N DPLL Using a Time-Invariant-Probability Modulator, Generating a Nonlinearity-Robust DTC-Control Word File

Seong, Taeho , Lee, Yongsun , Hwang, Chanwoong , Lee, Jeonghyun , Park, Hangi , Lee, Kyuho Jason , Choi, Jaehyouk

Conference Paper Issue Date2020-02-18 View26
An Ultra-Low-Jitter, mmW-Band Frequency Synthesizer Based on Digital Subsampling PLL Using Optimally Spaced Voltage Comparators File

Kim, Juyeop , Lim, Younghyun , Yoon, Heein , Lee, Yongsun , Park, Hangi , Cho, Yoonseo , Seong, Taeho , Choi, Jaehyouk

Article Issue Date2019-12 View29
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