Showing results 1 to 4 of 4
Issue Date | Title | Author(s) | Type | View |
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2013-11-20 | High-performance gate sizing with a signoff timer | Kahng, Andrew B.; Kang, Seokhyeong; Lee, Hyein; Markov, Igor L.; Thapar, Pankit | CONFERENCE | 28 |
2013-06-02 | Learning-Based Approximation of Interconnect Delay and Slew in Signoff Timing Tools | Kang, Seokhyeong; Kahng, Andrew B.; Lee, Hyein; Nath, Siddhartha; Wadhwani, Jyoti | CONFERENCE | 34 |
2020-10-20 | SchemaBoard: Supporting correct assembly of schematic circuits using dynamic in-situ visualization | Kim, Yoonji; Lee, Hyein; Prasad, Ramkrishna; Je, Seungwoo; Choi, Youngkyung; Ashbrook, Daniel; Oakley, Ian; Bianchi, Andrea | CONFERENCE | 14 |
2013-06-04 | Smart Non-Default Routing for Clock Power Reduction | Kahng, Andrew B.; Kang, Seokhyeong; Lee, Hyein | CONFERENCE | 23 |