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Showing results 1 to 4 of 4

Issue DateTitleAuthor(s)TypeView
2013-11-20High-performance gate sizing with a signoff timerKahng, Andrew B.; Kang, Seokhyeong; Lee, Hyein; Markov, Igor L.; Thapar, PankitCONFERENCE28
2013-06-02Learning-Based Approximation of Interconnect Delay and Slew in Signoff Timing ToolsKang, Seokhyeong; Kahng, Andrew B.; Lee, Hyein; Nath, Siddhartha; Wadhwani, JyotiCONFERENCE34
2020-10-20SchemaBoard: Supporting correct assembly of schematic circuits using dynamic in-situ visualizationKim, Yoonji; Lee, Hyein; Prasad, Ramkrishna; Je, Seungwoo; Choi, Youngkyung; Ashbrook, Daniel; Oakley, Ian; Bianchi, AndreaCONFERENCE14
2013-06-04Smart Non-Default Routing for Clock Power ReductionKahng, Andrew B.; Kang, Seokhyeong; Lee, HyeinCONFERENCE23
Showing results 1 to 4 of 4