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Showing results 1 to 11 of 11

A 0.1-1.5-GHz Wide Harmonic-Locking-Free Delay-Locked Loop Using an Exponential DAC File

Park, Suneui , Kim, Juyeop , Hwang, Chanwoong , Park, Hangi , Yoo, Seyeon , Seong, Taeho , Choi, Jaehyouk

Article Issue Date2019-08 View104
A 170MHz-Lock-In-Range and −253dB-FoMjitter 12-to-14.5GHz Subsampling PLL with a 150µW Frequency-Disturbance-Correcting Loop Using a Low-Power Unevenly Spaced Edge Generator File

Lim, Younghyun , Kim, Juyeop , Jo, Yongwoo , Bang, Jooeun , Yoo, Seyeon , Park, Hangi , Yoon, Heein , Choi, Jaehyouk

Conference Paper Issue Date2020-02-16 View105
A 320-fs RMS Jitter and-75-dBc Reference-Spur Ring-DCO-Based Digital PLL Using an Optimal-Threshold TDC File

Seong, Taeho , Lee, Yongsun , Yoo, Seyeon , Choi, Jaehyouk

Article Issue Date2019-09 View165
A Low-Jitter and Low-Fractional-Spur Ring-DCO-Based Fractional-N Digital PLL Using a DTC's Second-/Third-Order Nonlinearity Cancellation and a Probability-Density-Shaping Delta sigma M File

Hwang, Chanwoong , Park, Hangi , Lee, Yongsun , Seong, Taeho , Choi, Jaehyouk

Article Issue Date2022-09 View106
A Low-Jitter and Low-Reference-Spur Ring-VCO- Based Injection-Locked Clock Multiplier Using a Triple-Point Background Calibrator File

Yoo, Seyeon , Choi, Seojin , Lee, Yongsun , Seong, Taeho , Lim, Younghyun , Choi, Jaehyouk

Article Issue Date2021-01 View86
A Low-Jitter and Wide-Frequency-Range D-Band Frequency Synthesizer with a Subsampling PLL and a Harmonic-Boosting Frequency Multiplier File

Jung, Seohee , Kim, Jaeho , Bang, Jooeun , Lee, Sarang , Yoon, Heein , Choi, Jaehyouk

Article Issue Date2025-05 View254
A −58dBc-Worst-Fractional-Spur and −234dB-FoMjitter, 5.5GHz Ring-DCO-Based Fractional-N DPLL Using a Time-Invariant-Probability Modulator, Generating a Nonlinearity-Robust DTC-Control Word File

Seong, Taeho , Lee, Yongsun , Hwang, Chanwoong , Lee, Jeonghyun , Park, Hangi , Lee, Kyuho Jason , Choi, Jaehyouk

Conference Paper Issue Date2020-02-18 View125
An Ultra-Low Integrated-Phase-Noise 28-GHz LO Generator for 5G Transceivers Supporting Multiple Frequency Bands

Yoon, Heein , Park, Suneui , Kim, Juyeop , Choi, Jaehyouk

Conference Paper Issue Date2022-08-29 View67
An Ultra-Low-Jitter, mmW-Band Frequency Synthesizer Based on Digital Subsampling PLL Using Optimally Spaced Voltage Comparators File

Kim, Juyeop , Lim, Younghyun , Yoon, Heein , Lee, Yongsun , Park, Hangi , Cho, Yoonseo , Seong, Taeho , Choi, Jaehyouk

Article Issue Date2019-12 View126
PVT-Robust Ultra-Low-Jitter Clock Multipliers Using an Injection-Locking Technique File File

Kim, Mina

Thesis Issue Date2016-02 View100
ULTRA-LOW PHASE NOISE AND MULTIPLE FREQUENCY BAND FREQUENCY SYNTHESIZERS FOR 5G MOBILE SYSTEMS File File

Yoon, Heein

Thesis Issue Date2019-08 View84
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