Interface state-dependent synaptic characteristics of Pt/CeO2/Pt memristors controlled by post-deposition annealing

Abstract

Artificial synapses with analog resistance changes have been actively investigated since they are essential elements in brain-inspired neuromorphic systems. In this study, interface state-dependent artificial synaptic characteristics of analog, linear, and symmetric synaptic weight update are demonstrated in Pt/CeO2/Pt memristors controlled by post-deposition annealing of CeO2 layer. The devices with optimized annealing temperature, i.e., 400 and 500 degrees C-annealed devices, show reliable and analog-type resistance decrease upon applying positive voltage, and vice versa upon applying negative voltage. The resistance change emulates wide-range, linear, and symmetric potentiation and depression behaviors, as being tunable by the number of pulses and its amplitude. It also exhibits short-term and long-term plasticity with respect to pulse conditions. The conduction modes are fitted well with Schottky conduction controlled by interface energy barrier. In addition, negligible resistance changes are observed in reference device with SiO2 interfacial layers inserted at top and bottom Pt/CeO2 interfaces, i.e., Pt/SiO2/CeO2/SiO2/Pt device, supporting that the resistance change is associated with tunable Pt/ CeO2 interface states. It is concluded that the resistance change is induced by voltage-driven tuning of Pt/CeO2 interface states, and the control of these interfaces is crucial for reliable synaptic operations.